# 
# Synthesis run script generated by Vivado
# 

set TIME_start [clock seconds] 
proc create_report { reportName command } {
  set status "."
  append status $reportName ".fail"
  if { [file exists $status] } {
    eval file delete [glob $status]
  }
  send_msg_id runtcl-4 info "Executing : $command"
  set retval [eval catch { $command } msg]
  if { $retval != 0 } {
    set fp [open $status w]
    close $fp
    send_msg_id runtcl-5 warning "$msg"
  }
}
set_param xicom.use_bs_reader 1
set_msg_config -id {Synth 8-256} -limit 10000
set_msg_config -id {Synth 8-638} -limit 10000
create_project -in_memory -part xc7z010clg400-1

set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.cache/wt [current_project]
set_property parent.project_path C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.xpr [current_project]
set_property XPM_LIBRARIES XPM_CDC [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language VHDL [current_project]
set_property ip_output_repo c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
read_mem C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sprites/sprites.mem
read_vhdl -library xil_defaultlib {
  C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Diviseur.vhd
  C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneRGB_V1.vhd
  C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneSync.vhd
  C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd
  C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd
  C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd
}
read_vhdl -library ourTypes C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/types.vhd
read_vhdl -vhdl2008 -library xil_defaultlib {
  C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/RAMController.vhd
  C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd
  C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/spritesRom.vhd
}
read_ip -quiet c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xci
set_property used_in_implementation false [get_files -all c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0_board.xdc]
set_property used_in_implementation false [get_files -all c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc]
set_property used_in_implementation false [get_files -all c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0_ooc.xdc]

# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
  set_property used_in_implementation false $dcp
}
read_xdc C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc
set_property used_in_implementation false [get_files C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc]

read_xdc dont_touch.xdc
set_property used_in_implementation false [get_files dont_touch.xdc]
set_param ips.enableIPCacheLiteLoad 1
close [open __synthesis_is_running__ w]

synth_design -top VGA_top -part xc7z010clg400-1


# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef VGA_top.dcp
create_report "synth_1_synth_report_utilization_0" "report_utilization -file VGA_top_utilization_synth.rpt -pb VGA_top_utilization_synth.pb"
file delete __synthesis_is_running__
close [open __synthesis_is_complete__ w]