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-- Company: 
-- Engineer: 
-- 
-- Create Date: 16.11.2021 12:02:26
-- Design Name: 
-- Module Name: Gene_Position - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Gene_Position is
    Port ( up : in STD_LOGIC;
           down : in STD_LOGIC;
           left : in STD_LOGIC;
           right : in STD_LOGIC;
           clk: in STD_LOGIC;
           reset: in STD_LOGIC;
           PosX : out unsigned (9 downto 0);
           PosY : out unsigned (8 downto 0));
end Gene_Position;

architecture Behavioral of Gene_Position is
signal valPosX: unsigned (9 downto 0);
signal valPosY: unsigned (8 downto 0);

begin

process(up, down, left, right, valPosX, valPosY, clk, reset)
begin
    if (reset = '0') then
        valPosX <= to_unsigned(100, valPosX'length);
        valPosY <= to_unsigned(100, valPosY'length);
    else
        if (clk'event and clk='1') then
             if (up='1') then
                    valPosY <= valPosY + 1;
                    valPosX <= valPosX;
             elsif ( down='1') then
                    valPosY <= valPosY - 1;
                    valPosX <= valPosX;         
             elsif ( left='1') then
                     valPosX <= valPosX - 1;
                     valPosY <= valPosY;
             elsif ( right='1') then
                    valPosX <= valPosX + 1;
                    valPosY <= valPosY;
             else 
                valPosX <= valPosX;
                valPosY <= valPosY;
             end if;
         end if;
    end if;
end process;
PosX <= valPosX;
PosY <= valPosY;
end Behavioral;