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-- Company: 
-- Engineer: 
-- 
-- Create Date: 19.10.2017 08:16:09
-- Design Name: 
-- Module Name: GeneRGB_V1 - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity GeneRGB_V1 is
    Port ( X : in unsigned (9 downto 0);
           Y : in unsigned (8 downto 0);
           IMG : in STD_LOGIC;
           R : out STD_LOGIC_VECTOR (4 downto 0);
           G : out STD_LOGIC_VECTOR (5 downto 0);
           B : out STD_LOGIC_VECTOR (4 downto 0);
           snakePresent : in std_logic);
end GeneRGB_V1;

architecture Behavioral of GeneRGB_V1 is

begin

process(X,Y,IMG,snakePresent)
      begin
      if (IMG='0') then
            R<=(others=>'0');
            B<=(others=>'0');
            G<=(others=>'0');
      elsif ( snakePresent = '1' ) then
                            R<=(others=>'1');
                            B<=(others=>'1');
                            G<=(others=>'1');
                    else
                            R<=(others=>'0');
                            B<=(others=>'0');
                            G<=(others=>'0');
      end if;
     
      end process; 

end Behavioral;