*** Running vivado with args -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source clk_wiz_0.tcl -notrace Command: synth_design -top clk_wiz_0 -part xc7z010clg400-1 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' INFO: [Device 21-403] Loading part xc7z010clg400-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 7326 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 2197.395 ; gain = 0.000 ; free physical = 120 ; free virtual = 5844 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0' [/home/leo/test_clean/test_clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70] INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0_clk_wiz' [/home/leo/test_clean/test_clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68] INFO: [Synth 8-6157] synthesizing module 'IBUF' [/home/leo/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:32983] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-6155] done synthesizing module 'IBUF' (1#1) [/home/leo/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:32983] INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/home/leo/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:39998] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT_F bound to: 36.500000 - type: double Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string Parameter CLKIN1_PERIOD bound to: 8.000000 - type: double Parameter CLKIN2_PERIOD bound to: 0.000000 - type: double Parameter CLKOUT0_DIVIDE_F bound to: 36.500000 - type: double Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT4_CASCADE bound to: FALSE - type: string Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string Parameter COMPENSATION bound to: ZHOLD - type: string Parameter DIVCLK_DIVIDE bound to: 5 - type: integer Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 Parameter IS_PSEN_INVERTED bound to: 1'b0 Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 Parameter IS_PWRDWN_INVERTED bound to: 1'b0 Parameter IS_RST_INVERTED bound to: 1'b0 Parameter REF_JITTER1 bound to: 0.010000 - type: double Parameter REF_JITTER2 bound to: 0.010000 - type: double Parameter SS_EN bound to: FALSE - type: string Parameter SS_MODE bound to: CENTER_HIGH - type: string Parameter SS_MOD_PERIOD bound to: 10000 - type: integer Parameter STARTUP_WAIT bound to: FALSE - type: string INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (2#1) [/home/leo/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:39998] INFO: [Synth 8-6157] synthesizing module 'BUFG' [/home/leo/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:1083] INFO: [Synth 8-6155] done synthesizing module 'BUFG' (3#1) [/home/leo/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:1083] INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0_clk_wiz' (4#1) [/home/leo/test_clean/test_clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68] INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0' (5#1) [/home/leo/test_clean/test_clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 2197.395 ; gain = 0.000 ; free physical = 182 ; free virtual = 5844 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:15 . Memory (MB): peak = 2197.395 ; gain = 0.000 ; free physical = 94 ; free virtual = 5679 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:15 . Memory (MB): peak = 2197.395 ; gain = 0.000 ; free physical = 94 ; free virtual = 5679 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2197.395 ; gain = 0.000 ; free physical = 105 ; free virtual = 5687 INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/leo/test_clean/test_clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst' Finished Parsing XDC File [/home/leo/test_clean/test_clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst' Parsing XDC File [/home/leo/test_clean/test_clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst' Finished Parsing XDC File [/home/leo/test_clean/test_clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst' Parsing XDC File [/home/leo/test_clean/test_clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst' Finished Parsing XDC File [/home/leo/test_clean/test_clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/leo/test_clean/test_clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_wiz_0_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/clk_wiz_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Timing 38-2] Deriving generated clocks Parsing XDC File [/home/leo/test_clean/test_clean.runs/clk_wiz_0_synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/leo/test_clean/test_clean.runs/clk_wiz_0_synth_1/dont_touch.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2261.406 ; gain = 0.000 ; free physical = 837 ; free virtual = 5815 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2261.406 ; gain = 0.000 ; free physical = 826 ; free virtual = 5808 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:33 . Memory (MB): peak = 2261.406 ; gain = 64.012 ; free physical = 822 ; free virtual = 5877 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:33 . Memory (MB): peak = 2261.406 ; gain = 64.012 ; free physical = 822 ; free virtual = 5877 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /home/leo/test_clean/test_clean.runs/clk_wiz_0_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:33 . Memory (MB): peak = 2261.406 ; gain = 64.012 ; free physical = 822 ; free virtual = 5878 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:33 . Memory (MB): peak = 2261.406 ; gain = 64.012 ; free physical = 821 ; free virtual = 5878 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 80 (col length:40) BRAMs: 120 (col length: RAMB18 40 RAMB36 20) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:34 . Memory (MB): peak = 2261.406 ; gain = 64.012 ; free physical = 817 ; free virtual = 5879 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:43 . Memory (MB): peak = 2261.406 ; gain = 64.012 ; free physical = 626 ; free virtual = 5760 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:44 . Memory (MB): peak = 2261.406 ; gain = 64.012 ; free physical = 626 ; free virtual = 5759 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:26 ; elapsed = 00:00:44 . Memory (MB): peak = 2261.406 ; gain = 64.012 ; free physical = 623 ; free virtual = 5757 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:31 ; elapsed = 00:00:48 . Memory (MB): peak = 2261.406 ; gain = 64.012 ; free physical = 599 ; free virtual = 5752 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:31 ; elapsed = 00:00:48 . Memory (MB): peak = 2261.406 ; gain = 64.012 ; free physical = 599 ; free virtual = 5752 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:31 ; elapsed = 00:00:48 . Memory (MB): peak = 2261.406 ; gain = 64.012 ; free physical = 599 ; free virtual = 5752 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:31 ; elapsed = 00:00:48 . Memory (MB): peak = 2261.406 ; gain = 64.012 ; free physical = 599 ; free virtual = 5752 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:31 ; elapsed = 00:00:48 . Memory (MB): peak = 2261.406 ; gain = 64.012 ; free physical = 599 ; free virtual = 5752 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:31 ; elapsed = 00:00:48 . Memory (MB): peak = 2261.406 ; gain = 64.012 ; free physical = 599 ; free virtual = 5752 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----------+------+ | |Cell |Count | +------+-----------+------+ |1 |BUFG | 2| |2 |MMCME2_ADV | 1| |3 |IBUF | 1| +------+-----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:31 ; elapsed = 00:00:48 . Memory (MB): peak = 2261.406 ; gain = 64.012 ; free physical = 599 ; free virtual = 5752 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:27 ; elapsed = 00:00:37 . Memory (MB): peak = 2261.406 ; gain = 0.000 ; free physical = 648 ; free virtual = 5801 Synthesis Optimization Complete : Time (s): cpu = 00:00:31 ; elapsed = 00:00:48 . Memory (MB): peak = 2261.406 ; gain = 64.012 ; free physical = 648 ; free virtual = 5801 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2261.406 ; gain = 0.000 ; free physical = 642 ; free virtual = 5796 INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2261.406 ; gain = 0.000 ; free physical = 645 ; free virtual = 5818 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 28 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:59 . Memory (MB): peak = 2261.406 ; gain = 64.031 ; free physical = 762 ; free virtual = 5946 INFO: [Common 17-1381] The checkpoint '/home/leo/test_clean/test_clean.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP clk_wiz_0, cache-ID = 6e68fd1177c09e7d INFO: [Common 17-1381] The checkpoint '/home/leo/test_clean/test_clean.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Tue Jan 11 09:35:17 2022...