library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_textio.all; use std.textio.all; entity testbench is end testbench; architecture Behavioral of testbench is component VGA_top is Port ( H125MHz : in STD_LOGIC; resetGeneral : in std_logic; resetPomme : in std_logic; led : out std_logic_vector (3 downto 0); vga_hs : out STD_LOGIC; vga_vs : out STD_LOGIC; vga_r : out STD_LOGIC_VECTOR (4 downto 0); vga_g : out STD_LOGIC_VECTOR (5 downto 0); vga_b : out STD_LOGIC_VECTOR (4 downto 0); button_up : in STD_LOGIC; button_down : in STD_LOGIC; button_left : in STD_LOGIC; button_right : in STD_LOGIC ); end component; constant clk_period : time := 8 ns; signal clk : std_logic := '0'; signal HS : std_logic; signal VS : std_logic; signal R : STD_LOGIC_VECTOR (4 downto 0); signal G : STD_LOGIC_VECTOR (5 downto 0); signal B : STD_LOGIC_VECTOR (4 downto 0); begin U0 : VGA_top port map(H125MHz => clk, resetGeneral => '1', resetPomme => '1', led => open, vga_hs => HS, vga_vs => VS, vga_r => R, vga_g => G, vga_b => B, button_up => '0', button_down => '0', button_left => '0', button_right => '0' ); clk <= not clk after clk_period/2; process (clk) file file_pointer: text open write_mode is "write.txt"; variable line_el: line; begin if rising_edge(clk) then write(line_el, now); -- write the line. write(line_el, string'(":")); -- write the line. write(line_el, string'(" ")); write(line_el, HS); -- write the line. write(line_el, string'(" ")); write(line_el, VS); -- write the line. write(line_el, string'(" ")); write(line_el, R & '0'); -- write the line. write(line_el, string'(" ")); write(line_el, G); -- write the line. write(line_el, string'(" ")); write(line_el, B & '0'); -- write the line. writeline(file_pointer, line_el); -- write the contents into the file. end if; end process; end Behavioral;