Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Date : Tue Dec 7 12:43:48 2021 | Host : irb121-02-w running 64-bit major release (build 9200) | Command : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt | Design : VGA_top | Device : 7z010-clg400 | Speed File : -1 PRODUCTION 1.11 2014-09-11 ------------------------------------------------------------------------------------- Clock Utilization Report Table of Contents ----------------- 1. Clock Primitive Utilization 2. Global Clock Resources 3. Global Clock Source Details 4. Clock Regions: Key Resource Utilization 5. Clock Regions : Global Clock Summary 6. Device Cell Placement Summary for Global Clock g0 7. Device Cell Placement Summary for Global Clock g1 8. Clock Region Cell Placement per Global Clock: Region X1Y0 9. Clock Region Cell Placement per Global Clock: Region X1Y1 1. Clock Primitive Utilization ------------------------------ +----------+------+-----------+-----+--------------+--------+ | Type | Used | Available | LOC | Clock Region | Pblock | +----------+------+-----------+-----+--------------+--------+ | BUFGCTRL | 2 | 32 | 0 | 0 | 0 | | BUFH | 0 | 48 | 0 | 0 | 0 | | BUFIO | 0 | 8 | 0 | 0 | 0 | | BUFMR | 0 | 4 | 0 | 0 | 0 | | BUFR | 0 | 8 | 0 | 0 | 0 | | MMCM | 1 | 2 | 0 | 0 | 0 | | PLL | 0 | 2 | 0 | 0 | 0 | +----------+------+-----------+-----+--------------+--------+ 2. Global Clock Resources ------------------------- +-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+----------+-----------------------+--------------------------------+ | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+----------+-----------------------+--------------------------------+ | g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 2 | 21 | 0 | 40.000 | Multiple | U0/inst/clkout1_buf/O | U0/inst/clk_out1 | | g1 | src0 | BUFG/O | None | BUFGCTRL_X0Y17 | n/a | 1 | 1 | 0 | 40.000 | Multiple | U0/inst/clkf_buf/O | U0/inst/clkfbout_buf_clk_wiz_1 | +-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+----------+-----------------------+--------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) 3. Global Clock Source Details ------------------------------ +-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------+----------------------------+ | Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | +-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------+----------------------------+ | src0 | g0 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X0Y1 | X1Y1 | 1 | 0 | 40.000 | Multiple | U0/inst/mmcm_adv_inst/CLKOUT0 | U0/inst/clk_out1_clk_wiz_1 | | src0 | g1 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X0Y1 | X1Y1 | 1 | 0 | 40.000 | Multiple | U0/inst/mmcm_adv_inst/CLKFBOUT | U0/inst/clkfbout_clk_wiz_1 | +-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------+----------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) 4. Clock Regions: Key Resource Utilization ------------------------------------------ +-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ | | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | X0Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3 | 1100 | 1 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | | X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y1 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 18 | 1100 | 3 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ * Global Clock column represents track count; while other columns represents cell counts 5. Clock Regions : Global Clock Summary --------------------------------------- All Modules +----+----+----+ | | X0 | X1 | +----+----+----+ | Y1 | 0 | 2 | | Y0 | 0 | 1 | +----+----+----+ 6. Device Cell Placement Summary for Global Clock g0 ---------------------------------------------------- +-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+------------------+ | g0 | BUFG/O | n/a | Multiple | 40.000 | {0.000 20.000} | 21 | 0 | 0 | 0 | U0/inst/clk_out1 | +-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+-----+ | | X0 | X1 | +----+----+-----+ | Y1 | 0 | 18 | | Y0 | 0 | 3 | +----+----+-----+ 7. Device Cell Placement Summary for Global Clock g1 ---------------------------------------------------- +-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+ | g1 | BUFG/O | n/a | Multiple | 40.000 | {0.000 20.000} | 0 | 0 | 1 | 0 | U0/inst/clkfbout_buf_clk_wiz_1 | +-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+ | | X0 | X1 | +----+----+----+ | Y1 | 0 | 1 | | Y0 | 0 | 0 | +----+----+----+ 8. Clock Region Cell Placement per Global Clock: Region X1Y0 ------------------------------------------------------------ +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------+ | g0 | n/a | BUFG/O | None | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | U0/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 9. Clock Region Cell Placement per Global Clock: Region X1Y1 ------------------------------------------------------------ +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+ | g0 | n/a | BUFG/O | None | 18 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | U0/inst/clk_out1 | | g1 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | U0/inst/clkfbout_buf_clk_wiz_1 | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts # Location of BUFG Primitives set_property LOC BUFGCTRL_X0Y17 [get_cells U0/inst/clkf_buf] set_property LOC BUFGCTRL_X0Y16 [get_cells U0/inst/clkout1_buf] # Location of IO Primitives which is load of clock spine # Location of clock ports set_property LOC IOB_X0Y78 [get_ports H125MHz] # Clock net "U0/inst/clk_out1" driven by instance "U0/inst/clkout1_buf" located at site "BUFGCTRL_X0Y16" #startgroup create_pblock {CLKAG_U0/inst/clk_out1} add_cells_to_pblock [get_pblocks {CLKAG_U0/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="U0/inst/clk_out1"}]]] resize_pblock [get_pblocks {CLKAG_U0/inst/clk_out1}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1} #endgroup