Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
| Date         : Tue Dec  7 12:43:23 2021
| Host         : irb121-02-w running 64-bit major release  (build 9200)
| Command      : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
| Design       : VGA_top
| Device       : xc7z010
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets                            |     2 |
| Unused register locations in slices containing registers |    11 |
+----------------------------------------------------------+-------+


2. Histogram
------------

+--------+--------------+
| Fanout | Control Sets |
+--------+--------------+
|     10 |            1 |
|     11 |            1 |
+--------+--------------+


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |               0 |            0 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |              11 |            4 |
| Yes          | No                    | No                     |               0 |            0 |
| Yes          | No                    | Yes                    |               0 |            0 |
| Yes          | Yes                   | No                     |              10 |            5 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+-------------------+---------------+------------------+------------------+----------------+
|    Clock Signal   | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
+-------------------+---------------+------------------+------------------+----------------+
|  U0/inst/clk_out1 | U1/eqOp       | U1/comptY        |                5 |             10 |
|  U0/inst/clk_out1 |               | U1/clear         |                4 |             11 |
+-------------------+---------------+------------------+------------------+----------------+