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snake-vhdl/projet-electronique-clean/projet-electronique-clean.runs/clk_wiz_0_synth_1/runme.log
leo 61bf636a3f final
2022-01-11 13:06:04 +01:00

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*** Running vivado
with args -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl
****** Vivado v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source clk_wiz_0.tcl -notrace
Command: synth_design -top clk_wiz_0 -part xc7z010clg400-1 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'
INFO: [Device 21-403] Loading part xc7z010clg400-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 55768
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Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2275.867 ; gain = 0.000 ; free physical = 150 ; free virtual = 5468
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INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0' [/home/leo/ETN_snake/ETN_snake.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70]
INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0_clk_wiz' [/home/leo/ETN_snake/ETN_snake.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68]
INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/home/leo/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:39998]
Parameter BANDWIDTH bound to: OPTIMIZED - type: string
Parameter CLKFBOUT_MULT_F bound to: 36.500000 - type: double
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKIN1_PERIOD bound to: 8.000000 - type: double
Parameter CLKIN2_PERIOD bound to: 0.000000 - type: double
Parameter CLKOUT0_DIVIDE_F bound to: 36.500000 - type: double
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string
Parameter COMPENSATION bound to: ZHOLD - type: string
Parameter DIVCLK_DIVIDE bound to: 5 - type: integer
Parameter IS_CLKINSEL_INVERTED bound to: 1'b0
Parameter IS_PSEN_INVERTED bound to: 1'b0
Parameter IS_PSINCDEC_INVERTED bound to: 1'b0
Parameter IS_PWRDWN_INVERTED bound to: 1'b0
Parameter IS_RST_INVERTED bound to: 1'b0
Parameter REF_JITTER1 bound to: 0.010000 - type: double
Parameter REF_JITTER2 bound to: 0.010000 - type: double
Parameter SS_EN bound to: FALSE - type: string
Parameter SS_MODE bound to: CENTER_HIGH - type: string
Parameter SS_MOD_PERIOD bound to: 10000 - type: integer
Parameter STARTUP_WAIT bound to: FALSE - type: string
INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (1#1) [/home/leo/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:39998]
INFO: [Synth 8-6157] synthesizing module 'BUFG' [/home/leo/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:1083]
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (2#1) [/home/leo/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:1083]
INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0_clk_wiz' (3#1) [/home/leo/ETN_snake/ETN_snake.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68]
INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0' (4#1) [/home/leo/ETN_snake/ETN_snake.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70]
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Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 2275.867 ; gain = 0.000 ; free physical = 95 ; free virtual = 5040
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 2275.867 ; gain = 0.000 ; free physical = 112 ; free virtual = 4895
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 2275.867 ; gain = 0.000 ; free physical = 112 ; free virtual = 4895
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2275.867 ; gain = 0.000 ; free physical = 114 ; free virtual = 4898
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/leo/ETN_snake/ETN_snake.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst'
Finished Parsing XDC File [/home/leo/ETN_snake/ETN_snake.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst'
Parsing XDC File [/home/leo/ETN_snake/ETN_snake.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst'
Finished Parsing XDC File [/home/leo/ETN_snake/ETN_snake.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst'
Parsing XDC File [/home/leo/ETN_snake/ETN_snake.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst'
Finished Parsing XDC File [/home/leo/ETN_snake/ETN_snake.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst'
Parsing XDC File [/home/leo/ETN_snake/ETN_snake.runs/clk_wiz_0_synth_1/dont_touch.xdc]
Finished Parsing XDC File [/home/leo/ETN_snake/ETN_snake.runs/clk_wiz_0_synth_1/dont_touch.xdc]
Parsing XDC File [/home/leo/ETN_snake/ETN_snake.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_late.xdc] for cell 'inst'
Finished Parsing XDC File [/home/leo/ETN_snake/ETN_snake.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_late.xdc] for cell 'inst'
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2339.879 ; gain = 0.000 ; free physical = 715 ; free virtual = 5511
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Timing 38-2] Deriving generated clocks
Constraint Validation Runtime : Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2339.879 ; gain = 0.000 ; free physical = 714 ; free virtual = 5511
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Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:20 . Memory (MB): peak = 2339.879 ; gain = 64.012 ; free physical = 787 ; free virtual = 5588
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Start Loading Part and Timing Information
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Loading part: xc7z010clg400-1
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:20 . Memory (MB): peak = 2339.879 ; gain = 64.012 ; free physical = 787 ; free virtual = 5588
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Start Applying 'set_property' XDC Constraints
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Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /home/leo/ETN_snake/ETN_snake.runs/clk_wiz_0_synth_1/dont_touch.xdc, line 9).
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Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:20 . Memory (MB): peak = 2339.879 ; gain = 64.012 ; free physical = 787 ; free virtual = 5588
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:20 . Memory (MB): peak = 2339.879 ; gain = 64.012 ; free physical = 789 ; free virtual = 5591
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Start RTL Component Statistics
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Detailed RTL Component Info :
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Finished RTL Component Statistics
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Start Part Resource Summary
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Part Resources:
DSPs: 80 (col length:40)
BRAMs: 120 (col length: RAMB18 40 RAMB36 20)
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Finished Part Resource Summary
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Start Cross Boundary and Area Optimization
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Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:21 . Memory (MB): peak = 2339.879 ; gain = 64.012 ; free physical = 787 ; free virtual = 5592
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Start Applying XDC Timing Constraints
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Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 2339.879 ; gain = 64.012 ; free physical = 656 ; free virtual = 5469
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Start Timing Optimization
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Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 2339.879 ; gain = 64.012 ; free physical = 655 ; free virtual = 5469
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Start Technology Mapping
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Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 2339.879 ; gain = 64.012 ; free physical = 651 ; free virtual = 5465
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Start IO Insertion
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Start Flattening Before IO Insertion
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Finished Flattening Before IO Insertion
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Start Final Netlist Cleanup
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Finished Final Netlist Cleanup
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Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 2339.879 ; gain = 64.012 ; free physical = 650 ; free virtual = 5464
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Start Renaming Generated Instances
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Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 2339.879 ; gain = 64.012 ; free physical = 650 ; free virtual = 5464
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Start Rebuilding User Hierarchy
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 2339.879 ; gain = 64.012 ; free physical = 650 ; free virtual = 5464
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Start Renaming Generated Ports
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Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 2339.879 ; gain = 64.012 ; free physical = 650 ; free virtual = 5464
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 2339.879 ; gain = 64.012 ; free physical = 650 ; free virtual = 5464
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Start Renaming Generated Nets
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Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 2339.879 ; gain = 64.012 ; free physical = 650 ; free virtual = 5464
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Start Writing Synthesis Report
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Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-----------+------+
| |Cell |Count |
+------+-----------+------+
|1 |BUFG | 2|
|2 |MMCME2_ADV | 1|
+------+-----------+------+
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Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 2339.879 ; gain = 64.012 ; free physical = 650 ; free virtual = 5464
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Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2339.879 ; gain = 0.000 ; free physical = 705 ; free virtual = 5519
Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 2339.879 ; gain = 64.012 ; free physical = 705 ; free virtual = 5519
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2339.879 ; gain = 0.000 ; free physical = 699 ; free virtual = 5514
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2339.879 ; gain = 0.000 ; free physical = 734 ; free virtual = 5548
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2339.879 ; gain = 64.031 ; free physical = 873 ; free virtual = 5687
INFO: [Common 17-1381] The checkpoint '/home/leo/ETN_snake/ETN_snake.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated.
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP clk_wiz_0, cache-ID = 4ebd7f8b6ba52916
INFO: [Common 17-1381] The checkpoint '/home/leo/ETN_snake/ETN_snake.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sun Dec 19 15:35:39 2021...
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