166 lines
9.4 KiB
Plaintext
166 lines
9.4 KiB
Plaintext
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
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| Date : Tue Jan 11 11:43:33 2022
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| Host : LAPTOP-6KRNTV69 running 64-bit Ubuntu 20.04 LTS
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| Command : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
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| Design : VGA_top
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| Device : xc7z010clg400-1
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| Design State : routed
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| Grade : commercial
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| Process : typical
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| Characterization : Production
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Power Report
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Table of Contents
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-----------------
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1. Summary
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1.1 On-Chip Components
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1.2 Power Supply Summary
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1.3 Confidence Level
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2. Settings
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2.1 Environment
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2.2 Clock Constraints
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3. Detailed Reports
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3.1 By Hierarchy
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1. Summary
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----------
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+--------------------------+--------------+
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| Total On-Chip Power (W) | 0.298 |
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| Design Power Budget (W) | Unspecified* |
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| Power Budget Margin (W) | NA |
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| Dynamic (W) | 0.202 |
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| Device Static (W) | 0.097 |
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| Effective TJA (C/W) | 11.5 |
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| Max Ambient (C) | 81.6 |
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| Junction Temperature (C) | 28.4 |
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| Confidence Level | Low |
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| Setting File | --- |
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| Simulation Activity File | --- |
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| Design Nets Matched | NA |
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+--------------------------+--------------+
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* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
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1.1 On-Chip Components
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----------------------
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+----------------+-----------+----------+-----------+-----------------+
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| On-Chip | Power (W) | Used | Available | Utilization (%) |
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+----------------+-----------+----------+-----------+-----------------+
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| Clocks | 0.005 | 5 | --- | --- |
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| Slice Logic | 0.005 | 3201 | --- | --- |
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| LUT as Logic | 0.004 | 1970 | 17600 | 11.19 |
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| CARRY4 | <0.001 | 307 | 4400 | 6.98 |
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| Register | <0.001 | 353 | 35200 | 1.00 |
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| F7/F8 Muxes | <0.001 | 33 | 17600 | 0.19 |
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| Others | 0.000 | 29 | --- | --- |
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| Signals | 0.007 | 2447 | --- | --- |
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| Block RAM | 0.068 | 22.5 | 60 | 37.50 |
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| MMCM | 0.115 | 1 | 2 | 50.00 |
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| I/O | 0.002 | 28 | 100 | 28.00 |
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| Static Power | 0.097 | | | |
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| Total | 0.298 | | | |
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+----------------+-----------+----------+-----------+-----------------+
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1.2 Power Supply Summary
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------------------------
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+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
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| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
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+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
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| Vccint | 1.000 | 0.084 | 0.080 | 0.005 | NA | Unspecified | NA |
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| Vccaux | 1.800 | 0.070 | 0.064 | 0.006 | NA | Unspecified | NA |
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| Vcco33 | 3.300 | 0.001 | 0.000 | 0.001 | NA | Unspecified | NA |
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| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vccbram | 1.000 | 0.007 | 0.006 | 0.001 | NA | Unspecified | NA |
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| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vccpint | 1.000 | 0.018 | 0.000 | 0.018 | NA | Unspecified | NA |
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| Vccpaux | 1.800 | 0.010 | 0.000 | 0.010 | NA | Unspecified | NA |
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| Vccpll | 1.800 | 0.003 | 0.000 | 0.003 | NA | Unspecified | NA |
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| Vcco_ddr | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vcco_mio0 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vcco_mio1 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
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+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
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1.3 Confidence Level
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--------------------
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+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
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| User Input Data | Confidence | Details | Action |
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+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
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| Design implementation state | High | Design is routed | |
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| Clock nodes activity | High | User specified more than 95% of clocks | |
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| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
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| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
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| Device models | High | Device models are Production | |
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| Overall confidence level | Low | | |
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+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
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2. Settings
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-----------
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2.1 Environment
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---------------
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+-----------------------+------------------------+
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| Ambient Temp (C) | 25.0 |
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| ThetaJA (C/W) | 11.5 |
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| Airflow (LFM) | 250 |
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| Heat Sink | none |
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| ThetaSA (C/W) | 0.0 |
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| Board Selection | medium (10"x10") |
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| # of Board Layers | 8to11 (8 to 11 Layers) |
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| Board Temperature (C) | 25.0 |
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+-----------------------+------------------------+
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2.2 Clock Constraints
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---------------------
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+--------------------+----------------------------+-----------------+
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| Clock | Domain | Constraint (ns) |
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+--------------------+----------------------------+-----------------+
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| clk_out1_clk_wiz_0 | U0/inst/clk_out1_clk_wiz_0 | 40.0 |
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| clkfbout_clk_wiz_0 | U0/inst/clkfbout_clk_wiz_0 | 40.0 |
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| sys_clk_pin | H125MHz | 8.0 |
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+--------------------+----------------------------+-----------------+
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3. Detailed Reports
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-------------------
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3.1 By Hierarchy
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----------------
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+---------------+-----------+
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| Name | Power (W) |
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+---------------+-----------+
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| VGA_top | 0.202 |
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| APPLE | 0.001 |
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| RAMCTRL | 0.075 |
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| MAT_RAM | 0.027 |
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| SNAKE_RAM | 0.048 |
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| U0 | 0.115 |
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| inst | 0.115 |
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| UPD | 0.007 |
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+---------------+-----------+
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