420 lines
42 KiB
Plaintext
420 lines
42 KiB
Plaintext
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*** Running vivado
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with args -log VGA_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source VGA_top.tcl
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****** Vivado v2020.2 (64-bit)
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**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
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**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
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** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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source VGA_top.tcl -notrace
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Command: synth_design -top VGA_top -part xc7z010clg400-1
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Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'
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INFO: [Device 21-403] Loading part xc7z010clg400-1
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INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
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INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
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INFO: [Synth 8-7075] Helper process launched with PID 135594
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---------------------------------------------------------------------------------
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Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2203.398 ; gain = 0.000 ; free physical = 128 ; free virtual = 5220
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---------------------------------------------------------------------------------
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INFO: [Synth 8-638] synthesizing module 'VGA_top' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/VGA_top.vhd:54]
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INFO: [Synth 8-637] synthesizing blackbox instance 'U0' of component 'clk_wiz_0' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/VGA_top.vhd:290]
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INFO: [Synth 8-3491] module 'GeneSync' declared at '/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/GeneSync.vhd:8' bound to instance 'SYNC' of component 'GeneSync' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/VGA_top.vhd:308]
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INFO: [Synth 8-638] synthesizing module 'GeneSync' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/GeneSync.vhd:17]
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WARNING: [Synth 8-312] ignoring unsynthesizable construct: non-synthesizable procedure call [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/GeneSync.vhd:45]
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INFO: [Synth 8-256] done synthesizing module 'GeneSync' (1#1) [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/GeneSync.vhd:17]
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INFO: [Synth 8-3491] module 'GeneRGB_V1' declared at '/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/GeneRGB_V1.vhd:37' bound to instance 'RGB' of component 'GeneRGB_V1' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/VGA_top.vhd:317]
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INFO: [Synth 8-638] synthesizing module 'GeneRGB_V1' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/GeneRGB_V1.vhd:49]
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INFO: [Synth 8-256] done synthesizing module 'GeneRGB_V1' (2#1) [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/GeneRGB_V1.vhd:49]
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Parameter nbBits bound to: 25 - type: integer
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INFO: [Synth 8-3491] module 'Diviseur' declared at '/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/Diviseur.vhd:34' bound to instance 'UPD_CLK_DIV' of component 'Diviseur' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/VGA_top.vhd:329]
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INFO: [Synth 8-638] synthesizing module 'Diviseur' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/Diviseur.vhd:43]
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Parameter nbBits bound to: 25 - type: integer
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INFO: [Synth 8-256] done synthesizing module 'Diviseur' (3#1) [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/Diviseur.vhd:43]
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Parameter addressSize bound to: 11 - type: integer
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INFO: [Synth 8-3491] module 'Gene_Snake' declared at '/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/Gene_Snake.vhd:39' bound to instance 'SNAKE' of component 'Gene_Snake' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/VGA_top.vhd:343]
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INFO: [Synth 8-638] synthesizing module 'Gene_Snake' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/Gene_Snake.vhd:63]
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Parameter addressSize bound to: 11 - type: integer
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INFO: [Synth 8-226] default block is never used [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/Gene_Snake.vhd:100]
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INFO: [Synth 8-226] default block is never used [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/Gene_Snake.vhd:100]
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INFO: [Synth 8-226] default block is never used [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/Gene_Snake.vhd:100]
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INFO: [Synth 8-226] default block is never used [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/Gene_Snake.vhd:100]
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INFO: [Synth 8-226] default block is never used [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/Gene_Snake.vhd:100]
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INFO: [Synth 8-226] default block is never used [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/Gene_Snake.vhd:100]
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INFO: [Synth 8-226] default block is never used [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/Gene_Snake.vhd:100]
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INFO: [Synth 8-226] default block is never used [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/Gene_Snake.vhd:100]
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INFO: [Synth 8-226] default block is never used [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/Gene_Snake.vhd:100]
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INFO: [Synth 8-256] done synthesizing module 'Gene_Snake' (4#1) [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/Gene_Snake.vhd:63]
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Parameter snakeDataSize bound to: 24 - type: integer
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INFO: [Synth 8-3491] module 'RAMController' declared at '/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/RAMController.vhd:9' bound to instance 'RAMCTRL' of component 'RAMController' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/VGA_top.vhd:362]
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INFO: [Synth 8-638] synthesizing module 'RAMController' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/RAMController.vhd:37]
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Parameter snakeDataSize bound to: 24 - type: integer
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Parameter length bound to: 1200 - type: integer
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Parameter addressSize bound to: 11 - type: integer
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Parameter dataSize bound to: 24 - type: integer
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INFO: [Synth 8-3491] module 'snakeRam' declared at '/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/snakeRam.vhd:37' bound to instance 'SNAKE_RAM' of component 'snakeRam' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/RAMController.vhd:61]
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INFO: [Synth 8-638] synthesizing module 'snakeRam' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/snakeRam.vhd:54]
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Parameter length bound to: 1200 - type: integer
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Parameter addressSize bound to: 11 - type: integer
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Parameter dataSize bound to: 24 - type: integer
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INFO: [Synth 8-256] done synthesizing module 'snakeRam' (5#1) [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/snakeRam.vhd:54]
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Parameter length bound to: 1200 - type: integer
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Parameter addressSize bound to: 11 - type: integer
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Parameter dataSize bound to: 11 - type: integer
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INFO: [Synth 8-3491] module 'snakeRam' declared at '/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/snakeRam.vhd:37' bound to instance 'MAT_RAM' of component 'snakeRam' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/RAMController.vhd:79]
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INFO: [Synth 8-638] synthesizing module 'snakeRam__parameterized1' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/snakeRam.vhd:54]
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Parameter length bound to: 1200 - type: integer
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Parameter addressSize bound to: 11 - type: integer
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Parameter dataSize bound to: 11 - type: integer
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INFO: [Synth 8-256] done synthesizing module 'snakeRam__parameterized1' (5#1) [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/snakeRam.vhd:54]
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INFO: [Synth 8-256] done synthesizing module 'RAMController' (6#1) [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/RAMController.vhd:37]
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Parameter dataSize bound to: 24 - type: integer
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INFO: [Synth 8-3491] module 'updateSnake' declared at '/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/updateSnake.vhd:37' bound to instance 'UPD' of component 'updateSnake' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/VGA_top.vhd:387]
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INFO: [Synth 8-638] synthesizing module 'updateSnake' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/updateSnake.vhd:70]
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Parameter dataSize bound to: 24 - type: integer
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INFO: [Synth 8-256] done synthesizing module 'updateSnake' (7#1) [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/updateSnake.vhd:70]
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Parameter dataSize bound to: 24 - type: integer
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INFO: [Synth 8-3491] module 'pomme' declared at '/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/pomme.vhd:37' bound to instance 'APPLE' of component 'pomme' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/VGA_top.vhd:418]
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INFO: [Synth 8-638] synthesizing module 'pomme' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/pomme.vhd:65]
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Parameter dataSize bound to: 24 - type: integer
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INFO: [Synth 8-256] done synthesizing module 'pomme' (8#1) [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/pomme.vhd:65]
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Parameter addressSize bound to: 10 - type: integer
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Parameter length bound to: 768 - type: integer
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Parameter dataSize bound to: 24 - type: integer
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Parameter fileName bound to: /home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet-electronique/sprites/sprites.mem - type: string
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INFO: [Synth 8-3491] module 'spritesRom' declared at '/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/spritesRom.vhd:36' bound to instance 'ROM' of component 'spritesRom' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/VGA_top.vhd:437]
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INFO: [Synth 8-638] synthesizing module 'spritesRom' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/spritesRom.vhd:47]
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Parameter addressSize bound to: 10 - type: integer
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Parameter length bound to: 768 - type: integer
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Parameter dataSize bound to: 24 - type: integer
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Parameter fileName bound to: /home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet-electronique/sprites/sprites.mem - type: string
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INFO: [Synth 8-256] done synthesizing module 'spritesRom' (9#1) [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/spritesRom.vhd:47]
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Parameter addressSize bound to: 8 - type: integer
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Parameter length bound to: 256 - type: integer
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Parameter dataSize bound to: 24 - type: integer
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Parameter fileName bound to: /home/leo/projet-electronique/sprites/pomme.mem - type: string
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INFO: [Synth 8-3491] module 'spritesRom' declared at '/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/spritesRom.vhd:36' bound to instance 'POMMEROM' of component 'spritesRom' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/VGA_top.vhd:450]
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INFO: [Synth 8-638] synthesizing module 'spritesRom__parameterized1' [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/spritesRom.vhd:47]
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Parameter addressSize bound to: 8 - type: integer
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Parameter length bound to: 256 - type: integer
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Parameter dataSize bound to: 24 - type: integer
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Parameter fileName bound to: /home/leo/projet-electronique/sprites/pomme.mem - type: string
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INFO: [Synth 8-256] done synthesizing module 'spritesRom__parameterized1' (9#1) [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/spritesRom.vhd:47]
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INFO: [Synth 8-256] done synthesizing module 'VGA_top' (10#1) [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/sources_1/imports/leo/projet_vga_etn_sources/VGA_top.vhd:54]
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---------------------------------------------------------------------------------
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Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:15 . Memory (MB): peak = 2203.398 ; gain = 0.000 ; free physical = 815 ; free virtual = 5283
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Handling Custom Attributes
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 2203.398 ; gain = 0.000 ; free physical = 821 ; free virtual = 5300
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 2203.398 ; gain = 0.000 ; free physical = 821 ; free virtual = 5300
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---------------------------------------------------------------------------------
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Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2203.398 ; gain = 0.000 ; free physical = 809 ; free virtual = 5296
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Processing XDC Constraints
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Initializing timing engine
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Parsing XDC File [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'U0'
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Finished Parsing XDC File [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'U0'
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Parsing XDC File [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/constrs_1/imports/projet_vga_etn_sources/ZYBO_Master.xdc]
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Finished Parsing XDC File [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/constrs_1/imports/projet_vga_etn_sources/ZYBO_Master.xdc]
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/constrs_1/imports/projet_vga_etn_sources/ZYBO_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/VGA_top_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/VGA_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Completed Processing XDC Constraints
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2267.410 ; gain = 0.000 ; free physical = 660 ; free virtual = 5198
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2267.410 ; gain = 0.000 ; free physical = 659 ; free virtual = 5198
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---------------------------------------------------------------------------------
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Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 2267.410 ; gain = 64.012 ; free physical = 707 ; free virtual = 5266
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Loading Part and Timing Information
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---------------------------------------------------------------------------------
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Loading part: xc7z010clg400-1
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---------------------------------------------------------------------------------
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 2267.410 ; gain = 64.012 ; free physical = 707 ; free virtual = 5266
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Applying 'set_property' XDC Constraints
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---------------------------------------------------------------------------------
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Applied set_property KEEP_HIERARCHY = SOFT for U0. (constraint file auto generated constraint).
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---------------------------------------------------------------------------------
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Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 2267.410 ; gain = 64.012 ; free physical = 707 ; free virtual = 5266
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---------------------------------------------------------------------------------
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INFO: [Synth 8-3971] The signal "snakeRam:/mem_reg" was recognized as a true dual port RAM template.
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INFO: [Synth 8-3971] The signal "snakeRam__parameterized1:/mem_reg" was recognized as a true dual port RAM template.
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---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:30 . Memory (MB): peak = 2267.410 ; gain = 64.012 ; free physical = 660 ; free virtual = 5224
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start RTL Component Statistics
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---------------------------------------------------------------------------------
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Detailed RTL Component Info :
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+---Adders :
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2 Input 32 Bit Adders := 1
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3 Input 12 Bit Adders := 10
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2 Input 12 Bit Adders := 1
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2 Input 11 Bit Adders := 16
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3 Input 11 Bit Adders := 10
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2 Input 10 Bit Adders := 14
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3 Input 10 Bit Adders := 9
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2 Input 9 Bit Adders := 2
|
|
3 Input 8 Bit Adders := 1
|
|
2 Input 7 Bit Adders := 3
|
|
2 Input 6 Bit Adders := 4
|
|
2 Input 5 Bit Adders := 1
|
|
2 Input 4 Bit Adders := 1
|
|
+---Registers :
|
|
32 Bit Registers := 1
|
|
24 Bit Registers := 12
|
|
12 Bit Registers := 1
|
|
11 Bit Registers := 18
|
|
10 Bit Registers := 6
|
|
9 Bit Registers := 3
|
|
8 Bit Registers := 3
|
|
6 Bit Registers := 3
|
|
5 Bit Registers := 6
|
|
4 Bit Registers := 1
|
|
1 Bit Registers := 15
|
|
+---RAMs :
|
|
28K Bit (1200 X 24 bit) RAMs := 1
|
|
12K Bit (1200 X 11 bit) RAMs := 1
|
|
+---Muxes :
|
|
2 Input 24 Bit Muxes := 5
|
|
769 Input 24 Bit Muxes := 1
|
|
2 Input 19 Bit Muxes := 1
|
|
2 Input 12 Bit Muxes := 10
|
|
2 Input 11 Bit Muxes := 22
|
|
4 Input 11 Bit Muxes := 1
|
|
2 Input 10 Bit Muxes := 48
|
|
257 Input 10 Bit Muxes := 1
|
|
2 Input 9 Bit Muxes := 4
|
|
2 Input 8 Bit Muxes := 4
|
|
2 Input 7 Bit Muxes := 1
|
|
2 Input 6 Bit Muxes := 5
|
|
2 Input 5 Bit Muxes := 13
|
|
7 Input 5 Bit Muxes := 1
|
|
2 Input 4 Bit Muxes := 3
|
|
6 Input 4 Bit Muxes := 1
|
|
3 Input 4 Bit Muxes := 1
|
|
11 Input 3 Bit Muxes := 1
|
|
2 Input 2 Bit Muxes := 5
|
|
5 Input 2 Bit Muxes := 3
|
|
8 Input 2 Bit Muxes := 1
|
|
2 Input 1 Bit Muxes := 64
|
|
9 Input 1 Bit Muxes := 2
|
|
11 Input 1 Bit Muxes := 1
|
|
10 Input 1 Bit Muxes := 1
|
|
4 Input 1 Bit Muxes := 5
|
|
8 Input 1 Bit Muxes := 3
|
|
3 Input 1 Bit Muxes := 2
|
|
7 Input 1 Bit Muxes := 1
|
|
6 Input 1 Bit Muxes := 4
|
|
5 Input 1 Bit Muxes := 4
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Part Resource Summary
|
|
---------------------------------------------------------------------------------
|
|
Part Resources:
|
|
DSPs: 80 (col length:40)
|
|
BRAMs: 120 (col length: RAMB18 40 RAMB36 20)
|
|
---------------------------------------------------------------------------------
|
|
Finished Part Resource Summary
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Cross Boundary and Area Optimization
|
|
---------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3971] The signal "RAMCTRL/SNAKE_RAM/mem_reg" was recognized as a true dual port RAM template.
|
|
INFO: [Synth 8-3971] The signal "RAMCTRL/MAT_RAM/mem_reg" was recognized as a true dual port RAM template.
|
|
---------------------------------------------------------------------------------
|
|
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:35 ; elapsed = 00:00:49 . Memory (MB): peak = 2267.410 ; gain = 64.012 ; free physical = 601 ; free virtual = 5226
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
|
|
---------------------------------------------------------------------------------
|
|
|
|
Block RAM: Preliminary Mapping Report (see note below)
|
|
-------NONE-------
|
|
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
|
|
---------------------------------------------------------------------------------
|
|
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Applying XDC Timing Constraints
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:41 ; elapsed = 00:00:55 . Memory (MB): peak = 2267.410 ; gain = 64.012 ; free physical = 481 ; free virtual = 5121
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Timing Optimization
|
|
---------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3971] The signal "RAMCTRL/SNAKE_RAM/mem_reg" was recognized as a true dual port RAM template.
|
|
---------------------------------------------------------------------------------
|
|
Finished Timing Optimization : Time (s): cpu = 00:00:47 ; elapsed = 00:01:01 . Memory (MB): peak = 2268.488 ; gain = 65.090 ; free physical = 404 ; free virtual = 5080
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
|
|
---------------------------------------------------------------------------------
|
|
|
|
Block RAM: Final Mapping Report
|
|
-------NONE-------
|
|
---------------------------------------------------------------------------------
|
|
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Technology Mapping
|
|
---------------------------------------------------------------------------------
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_2_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_2_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_4_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_4_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_5_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_5_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_6_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_6_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_7_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_7_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_8_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_8_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_9_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_9_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
INFO: [Synth 8-7052] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_9 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
|
|
---------------------------------------------------------------------------------
|
|
Finished Technology Mapping : Time (s): cpu = 00:00:49 ; elapsed = 00:01:03 . Memory (MB): peak = 2284.504 ; gain = 81.105 ; free physical = 392 ; free virtual = 5069
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Flattening Before IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Flattening Before IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Final Netlist Cleanup
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Final Netlist Cleanup
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished IO Insertion : Time (s): cpu = 00:00:52 ; elapsed = 00:01:06 . Memory (MB): peak = 2284.504 ; gain = 81.105 ; free physical = 375 ; free virtual = 5064
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Instances
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Instances : Time (s): cpu = 00:00:52 ; elapsed = 00:01:06 . Memory (MB): peak = 2284.504 ; gain = 81.105 ; free physical = 375 ; free virtual = 5064
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Rebuilding User Hierarchy
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:52 ; elapsed = 00:01:06 . Memory (MB): peak = 2284.504 ; gain = 81.105 ; free physical = 367 ; free virtual = 5057
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Ports
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Ports : Time (s): cpu = 00:00:52 ; elapsed = 00:01:06 . Memory (MB): peak = 2284.504 ; gain = 81.105 ; free physical = 367 ; free virtual = 5057
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Handling Custom Attributes
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:52 ; elapsed = 00:01:06 . Memory (MB): peak = 2284.504 ; gain = 81.105 ; free physical = 367 ; free virtual = 5057
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Nets
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Nets : Time (s): cpu = 00:00:52 ; elapsed = 00:01:06 . Memory (MB): peak = 2284.504 ; gain = 81.105 ; free physical = 367 ; free virtual = 5057
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Writing Synthesis Report
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report BlackBoxes:
|
|
+------+--------------+----------+
|
|
| |BlackBox name |Instances |
|
|
+------+--------------+----------+
|
|
|1 |clk_wiz_0 | 1|
|
|
+------+--------------+----------+
|
|
|
|
Report Cell Usage:
|
|
+------+---------------+------+
|
|
| |Cell |Count |
|
|
+------+---------------+------+
|
|
|1 |clk_wiz_0_bbox | 1|
|
|
|2 |BUFG | 1|
|
|
|3 |CARRY4 | 307|
|
|
|4 |LUT1 | 33|
|
|
|5 |LUT2 | 472|
|
|
|6 |LUT3 | 399|
|
|
|7 |LUT4 | 495|
|
|
|8 |LUT5 | 436|
|
|
|9 |LUT6 | 606|
|
|
|10 |MUXF7 | 32|
|
|
|11 |MUXF8 | 1|
|
|
|12 |RAMB18E1 | 9|
|
|
|13 |RAMB36E1 | 18|
|
|
|15 |FDCE | 61|
|
|
|16 |FDPE | 4|
|
|
|17 |FDRE | 276|
|
|
|18 |FDSE | 9|
|
|
|19 |LDC | 1|
|
|
|20 |IBUF | 6|
|
|
|21 |OBUF | 22|
|
|
+------+---------------+------+
|
|
---------------------------------------------------------------------------------
|
|
Finished Writing Synthesis Report : Time (s): cpu = 00:00:52 ; elapsed = 00:01:06 . Memory (MB): peak = 2284.504 ; gain = 81.105 ; free physical = 367 ; free virtual = 5057
|
|
---------------------------------------------------------------------------------
|
|
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
|
|
Synthesis Optimization Runtime : Time (s): cpu = 00:00:49 ; elapsed = 00:01:00 . Memory (MB): peak = 2284.504 ; gain = 17.094 ; free physical = 426 ; free virtual = 5117
|
|
Synthesis Optimization Complete : Time (s): cpu = 00:00:52 ; elapsed = 00:01:06 . Memory (MB): peak = 2284.512 ; gain = 81.105 ; free physical = 426 ; free virtual = 5117
|
|
INFO: [Project 1-571] Translating synthesized netlist
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2284.512 ; gain = 0.000 ; free physical = 423 ; free virtual = 5124
|
|
INFO: [Netlist 29-17] Analyzing 368 Unisim elements for replacement
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2316.520 ; gain = 0.000 ; free physical = 394 ; free virtual = 5162
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
A total of 1 instances were transformed.
|
|
LDC => LDCE: 1 instance
|
|
|
|
INFO: [Common 17-83] Releasing license: Synthesis
|
|
95 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
synth_design completed successfully
|
|
synth_design: Time (s): cpu = 00:01:04 ; elapsed = 00:01:20 . Memory (MB): peak = 2316.520 ; gain = 113.141 ; free physical = 551 ; free virtual = 5320
|
|
INFO: [Common 17-1381] The checkpoint '/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.runs/synth_1/VGA_top.dcp' has been generated.
|
|
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_synth.rpt -pb VGA_top_utilization_synth.pb
|
|
INFO: [Common 17-206] Exiting Vivado at Tue Jan 11 11:40:19 2022...
|