11 lines
369 B
Plaintext
11 lines
369 B
Plaintext
# compile verilog/system verilog design source files
|
|
verilog xil_defaultlib --include "../../../../ETN_snake.gen/sources_1/ip/clk_wiz_0" \
|
|
"../../../../ETN_snake.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \
|
|
"../../../../ETN_snake.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \
|
|
|
|
# compile glbl module
|
|
verilog xil_defaultlib "glbl.v"
|
|
|
|
# Do not sort compile order
|
|
nosort
|