32 lines
1.3 KiB
VHDL
32 lines
1.3 KiB
VHDL
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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-- --------------------------------------------------------------------------------
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-- Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
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-- Date : Tue Nov 9 11:11:50 2021
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-- Host : irb121-03-w running 64-bit major release (build 9200)
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-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.vhdl
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-- Design : clk_wiz_0
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-- Purpose : Stub declaration of top-level module interface
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-- Device : xc7z010clg400-1
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-- --------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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Port (
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clk_out1 : out STD_LOGIC;
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reset : in STD_LOGIC;
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locked : out STD_LOGIC;
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clk_in1 : in STD_LOGIC
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);
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end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
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architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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attribute syn_black_box : boolean;
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attribute black_box_pad_pin : string;
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attribute syn_black_box of stub : architecture is true;
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attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1";
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begin
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end;
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