21 lines
1.2 KiB
Verilog
21 lines
1.2 KiB
Verilog
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
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// Date : Tue Nov 16 10:40:09 2021
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// Host : irb121-03-w running 64-bit major release (build 9200)
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// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_1_stub.v
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// Design : clk_wiz_1
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7z010clg400-1
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// --------------------------------------------------------------------------------
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk_out1, clk_in1)
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/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_in1" */;
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output clk_out1;
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input clk_in1;
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endmodule
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