103 lines
7.3 KiB
Plaintext
103 lines
7.3 KiB
Plaintext
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
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| Date : Tue Jan 4 12:19:29 2022
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| Host : irb121-12-w running 64-bit major release (build 9200)
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| Command : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
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| Design : VGA_top
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| Device : xc7z010
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------------------------------------------------------------------------------------
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Control Set Information
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Table of Contents
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-----------------
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1. Summary
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2. Histogram
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3. Flip-Flop Distribution
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4. Detailed Control Set Information
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1. Summary
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----------
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+----------------------------------------------------------+-------+
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| Status | Count |
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+----------------------------------------------------------+-------+
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| Number of unique control sets | 31 |
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| Unused register locations in slices containing registers | 180 |
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+----------------------------------------------------------+-------+
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2. Histogram
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------------
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+--------+--------------+
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| Fanout | Control Sets |
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+--------+--------------+
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| 1 | 17 |
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| 3 | 2 |
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| 4 | 2 |
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| 10 | 2 |
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| 11 | 2 |
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| 13 | 1 |
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| 14 | 1 |
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| 16+ | 4 |
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+--------+--------------+
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3. Flip-Flop Distribution
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-------------------------
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+--------------+-----------------------+------------------------+-----------------+--------------+
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| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
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+--------------+-----------------------+------------------------+-----------------+--------------+
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| No | No | No | 71 | 29 |
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| No | No | Yes | 40 | 13 |
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| No | Yes | No | 34 | 21 |
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| Yes | No | No | 25 | 12 |
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| Yes | No | Yes | 32 | 18 |
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| Yes | Yes | No | 10 | 6 |
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+--------------+-----------------------+------------------------+-----------------+--------------+
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4. Detailed Control Set Information
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-----------------------------------
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+----------------------------------+------------------------+---------------------------------------+------------------+----------------+
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| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
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+----------------------------------+------------------------+---------------------------------------+------------------+----------------+
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| U0/inst/clk_out1 | | SNAKE/startUpdate_i_2_n_0 | 1 | 1 |
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| UPD/dataOut_reg[19]_LDC_i_1_n_0 | | UPD/dataOut_reg[19]_LDC_i_2_n_0 | 1 | 1 |
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| UPD/dataOut_reg[18]_LDC_i_1_n_0 | | UPD/dataOut_reg[18]_LDC_i_2_n_0 | 1 | 1 |
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| UPD/dataOut_reg[1]_LDC_i_1_n_0 | | UPD/dataOut_reg[1]_LDC_i_2_n_0 | 1 | 1 |
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| UPD/dataOut_reg[4]_LDC_i_1_n_0 | | UPD/dataOut_reg[4]_LDC_i_2_n_0 | 1 | 1 |
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| UPD/dataOut_reg[21]_LDC_i_1_n_0 | | UPD/dataOut_reg[21]_LDC_i_2_n_0 | 1 | 1 |
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| UPD/dataOut_reg[20]_LDC_i_1_n_0 | | UPD/dataOut_reg[20]_LDC_i_2_n_0 | 1 | 1 |
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| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[19]_LDC_i_1_n_0 | 1 | 1 |
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| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[18]_LDC_i_1_n_0 | 1 | 1 |
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| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[1]_LDC_i_1_n_0 | 1 | 1 |
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| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[21]_LDC_i_2_n_0 | 1 | 1 |
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| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[21]_LDC_i_1_n_0 | 1 | 1 |
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| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[20]_LDC_i_2_n_0 | 1 | 1 |
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| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[18]_LDC_i_2_n_0 | 1 | 1 |
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| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[19]_LDC_i_2_n_0 | 1 | 1 |
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| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[20]_LDC_i_1_n_0 | 1 | 1 |
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| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[1]_LDC_i_2_n_0 | 1 | 1 |
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| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[4]_LDC_i_1_n_0 | 1 | 3 |
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| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[4]_LDC_i_2_n_0 | 1 | 3 |
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| H125MHz_IBUF_BUFG | | SNAKE/Q[0] | 4 | 4 |
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| H125MHz_IBUF_BUFG | UPD/update | | 2 | 4 |
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| U0/inst/clk_out1 | SYNC/eqOp | SYNC/comptY | 6 | 10 |
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| H125MHz_IBUF_BUFG | RAMCTRL/SNAKE_RAM/E[0] | | 3 | 10 |
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| U0/inst/clk_out1 | | SYNC/clear | 6 | 11 |
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| H125MHz_IBUF_BUFG | SNAKE/cCaseX0 | | 7 | 11 |
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| U0/inst/clk_out1 | | SNAKE/AR[0] | 4 | 13 |
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| H125MHz_IBUF_BUFG | | SNAKE/AR[0] | 6 | 14 |
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| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/currentSnake_reg[dirY][0]_i_2_n_0 | 6 | 16 |
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| ~UPD/update | | | 5 | 17 |
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| U0/inst/clk_out1 | | UPD_CLK_DIV/temp[0]_i_2_n_0 | 7 | 25 |
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| H125MHz_IBUF_BUFG | | | 24 | 54 |
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+----------------------------------+------------------------+---------------------------------------+------------------+----------------+
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