42 lines
1.5 KiB
Plaintext
42 lines
1.5 KiB
Plaintext
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
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| Date : Tue Jan 4 12:19:12 2022
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| Host : irb121-12-w running 64-bit major release (build 9200)
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| Command : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
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| Design : VGA_top
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| Device : xc7z010clg400-1
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| Speed File : -1
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| Design State : Synthesized
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Report DRC
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Table of Contents
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-----------------
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1. REPORT SUMMARY
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2. REPORT DETAILS
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1. REPORT SUMMARY
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-----------------
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Netlist: netlist
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Floorplan: design_1
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Design limits: <entire design considered>
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Ruledeck: default
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Max violations: <unlimited>
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Violations found: 1
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+--------+----------+--------------------+------------+
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| Rule | Severity | Description | Violations |
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+--------+----------+--------------------+------------+
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| ZPS7-1 | Warning | PS7 block required | 1 |
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+--------+----------+--------------------+------------+
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2. REPORT DETAILS
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-----------------
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ZPS7-1#1 Warning
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PS7 block required
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The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
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Related violations: <none>
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