80 lines
2.1 KiB
VHDL
80 lines
2.1 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 16.11.2021 12:02:26
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-- Design Name:
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-- Module Name: Gene_Position - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Gene_Position is
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Port ( up : in STD_LOGIC;
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down : in STD_LOGIC;
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left : in STD_LOGIC;
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right : in STD_LOGIC;
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clk: in STD_LOGIC;
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reset: in STD_LOGIC;
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PosX : out unsigned (9 downto 0);
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PosY : out unsigned (8 downto 0));
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end Gene_Position;
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architecture Behavioral of Gene_Position is
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signal valPosX: unsigned (9 downto 0);
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signal valPosY: unsigned (8 downto 0);
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begin
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process(up, down, left, right, valPosX, valPosY, clk, reset)
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begin
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if (reset = '0') then
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valPosX <= to_unsigned(100, valPosX'length);
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valPosY <= to_unsigned(100, valPosY'length);
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else
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if (clk'event and clk='1') then
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if (up='1') then
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valPosY <= valPosY + 1;
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valPosX <= valPosX;
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elsif ( down='1') then
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valPosY <= valPosY - 1;
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valPosX <= valPosX;
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elsif ( left='1') then
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valPosX <= valPosX - 1;
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valPosY <= valPosY;
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elsif ( right='1') then
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valPosX <= valPosX + 1;
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valPosY <= valPosY;
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else
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valPosX <= valPosX;
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valPosY <= valPosY;
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end if;
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end if;
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end if;
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end process;
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PosX <= valPosX;
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PosY <= valPosY;
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end Behavioral;
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