110 lines
2.1 KiB
VHDL
110 lines
2.1 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use std.textio.all;
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entity GeneSync is
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Port ( CLK : in std_logic;
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HSYNC : out std_logic;
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VSYNC : out std_logic;
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IMG : out std_logic;
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X : out std_logic_vector(9 downto 0);
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Y : out std_logic_vector(8 downto 0));
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end GeneSync;
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architecture Behavioral of GeneSync is
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signal comptX : std_logic_vector (10 downto 0) := (others => '0');
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signal comptY : std_logic_vector (9 downto 0) := (others => '0');
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signal Yaux : std_logic_vector (9 downto 0) := (others => '0');
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signal pulseX : std_logic;
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signal pulseY: std_logic;
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signal IMGX : std_logic;
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signal IMGY : std_logic;
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signal frameCount : integer := 0;
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begin
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Y<=Yaux(8 downto 0);
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HSYNC<=pulseX;
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VSYNC<=pulseY;
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IMG<=IMGX AND IMGY;
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process (clk)
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begin
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if (CLK'event and CLK='1')then
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if comptX(10 downto 0)<800 then
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comptX<=comptX+1;
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else
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comptX<="00000000000";
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end if;
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if comptX=0 then
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if comptY<521 then
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comptY<=comptY+1;
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else
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comptY<="0000000000";
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frameCount <= frameCount + 1;
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--std.env.stop; --end the simulation
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end if;
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end if;
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end if;
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end process;
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process (comptX)
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begin
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if (comptX(10 downto 0)<96) then
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X<="0000000000";
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pulseX<='0';
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IMGX<='0';
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else
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if (comptX(10 downto 0)<(96+48)) then
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X<="0000000000";
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pulseX<='1';
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IMGX<='0';
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else
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if (comptX(10 downto 0)<(96+48+640)) then
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X<=comptX(9 downto 0)-96-48;
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IMGX<='1';
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pulseX<='1';
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else
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X<="0000000000";
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pulseX<='1';
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IMGX<='0';
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end if;
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end if;
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end if;
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end process;
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process (comptY,Yaux)
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variable l : line;
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begin
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if (comptY<2) then
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Yaux<="0000000000";
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pulseY<='0';
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IMGY <= '0';
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else
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if (comptY<(2+29)) then
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Yaux<="0000000000";
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pulseY<='1';
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IMGY<='0';
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else
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if (comptY<(2+29+480)) then
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Yaux<=comptY-2-29;
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--write (l, Yaux);
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--writeline (output, l);
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pulseY<='1';
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IMGY<='1';
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else
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Yaux<="0000000000";
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pulseY<='1';
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IMGY<='0';
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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