67 lines
1.7 KiB
VHDL
67 lines
1.7 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 19.10.2017 08:16:09
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-- Design Name:
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-- Module Name: GeneRGB_V1 - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity GeneRGB_V1 is
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Port ( X : in unsigned (9 downto 0);
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Y : in unsigned (8 downto 0);
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IMG : in STD_LOGIC;
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R : out STD_LOGIC_VECTOR (4 downto 0);
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G : out STD_LOGIC_VECTOR (5 downto 0);
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B : out STD_LOGIC_VECTOR (4 downto 0);
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snakePresent : in std_logic);
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end GeneRGB_V1;
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architecture Behavioral of GeneRGB_V1 is
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begin
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process(X,Y,IMG,snakePresent)
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begin
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if (IMG='0') then
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R<=(others=>'0');
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B<=(others=>'0');
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G<=(others=>'0');
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elsif ( snakePresent = '1' ) then
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R<=(others=>'1');
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B<=(others=>'1');
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G<=(others=>'1');
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else
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R<=(others=>'0');
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B<=(others=>'0');
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G<=(others=>'0');
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end if;
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end process;
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end Behavioral;
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