76 lines
2.0 KiB
VHDL
76 lines
2.0 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12/15/2021 02:06:27 PM
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-- Design Name:
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-- Module Name: updateSnake - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library ourTypes;
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use ourTypes.types.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity updateSnake is
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Port ( inSnake : in pos;
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outSnake : out pos;
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inIndex : in unsigned(10 downto 0);
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outIndex : out unsigned(10 downto 0));
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end updateSnake;
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architecture Behavioral of updateSnake is
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signal cSnake : pos;
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begin
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process(inSnake)
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variable dir : direction;
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begin
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case inSnake.dir is
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when gauche =>
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cSnake.X <= inSnake.X - 1;
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cSnake.Y <= inSnake.Y;
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cSnake.dir <= inSnake.dir;
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cSnake.isDefined <= inSnake.isDefined;
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when droite =>
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cSnake.X <= inSnake.X + 1;
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cSnake.Y <= inSnake.Y;
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cSnake.dir <= inSnake.dir;
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cSnake.isDefined <= inSnake.isDefined;
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when haut =>
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cSnake.X <= inSnake.X;
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cSnake.Y <= inSnake.Y - 1;
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cSnake.dir <= inSnake.dir;
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cSnake.isDefined <= inSnake.isDefined;
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when bas =>
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cSnake.X <= inSnake.X;
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cSnake.Y <= inSnake.Y + 1;
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cSnake.dir <= inSnake.dir;
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cSnake.isDefined <= inSnake.isDefined;
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end case;
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end process;
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outSnake <= cSnake;
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outIndex <= inIndex + 1;
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end Behavioral;
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