546 lines
32 KiB
Plaintext
546 lines
32 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Tue Nov 23 10:08:25 2021
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# Process ID: 4688
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# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
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# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
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# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
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# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
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#-----------------------------------------------------------
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source VGA_top.tcl -notrace
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Command: link_design -top VGA_top -part xc7z010clg400-1
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Design is defaulting to srcset: sources_1
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Design is defaulting to constrset: constrs_1
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INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
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INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
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INFO: [Project 1-479] Netlist was created with Vivado 2018.3
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INFO: [Device 21-403] Loading part xc7z010clg400-1
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
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Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
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Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
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INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
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INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
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get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1242.828 ; gain = 551.719
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Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
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Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
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Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1242.828 ; gain = 0.000
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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link_design completed successfully
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link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:24 . Memory (MB): peak = 1242.828 ; gain = 879.852
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Command: opt_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
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Running DRC as a precondition to command opt_design
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Starting DRC Task
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Project 1-461] DRC finished with 0 Errors
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INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.501 . Memory (MB): peak = 1242.828 ; gain = 0.000
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Starting Cache Timing Information Task
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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INFO: [Timing 38-2] Deriving generated clocks
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Ending Cache Timing Information Task | Checksum: b8ea7a4e
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1260.746 ; gain = 17.918
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Starting Logic Optimization Task
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Phase 1 Retarget
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Opt 31-49] Retargeted 0 cell(s).
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Phase 1 Retarget | Checksum: b8ea7a4e
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1347.707 ; gain = 0.000
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INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
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INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
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Phase 2 Constant propagation
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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Phase 2 Constant propagation | Checksum: b8ea7a4e
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1347.707 ; gain = 0.000
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INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
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Phase 3 Sweep
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Phase 3 Sweep | Checksum: 69d8ab95
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1347.707 ; gain = 0.000
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INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
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Phase 4 BUFG optimization
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INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
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INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
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Phase 4 BUFG optimization | Checksum: 13bee9dc1
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1347.707 ; gain = 0.000
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INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
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Phase 5 Shift Register Optimization
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Phase 5 Shift Register Optimization | Checksum: 1a59d5459
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1347.707 ; gain = 0.000
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INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
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Phase 6 Post Processing Netlist
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Phase 6 Post Processing Netlist | Checksum: 14a40c514
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1347.707 ; gain = 0.000
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INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
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Opt_design Change Summary
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=========================
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-------------------------------------------------------------------------------------------------------------------------
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| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
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-------------------------------------------------------------------------------------------------------------------------
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| Retarget | 0 | 0 | 1 |
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| Constant propagation | 0 | 0 | 0 |
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| Sweep | 0 | 0 | 0 |
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| BUFG optimization | 0 | 0 | 0 |
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| Shift Register Optimization | 0 | 0 | 0 |
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| Post Processing Netlist | 0 | 0 | 0 |
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-------------------------------------------------------------------------------------------------------------------------
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Starting Connectivity Check Task
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Ending Logic Optimization Task | Checksum: 14dbbd0bc
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Starting Power Optimization Task
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INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
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Ending Power Optimization Task | Checksum: 14dbbd0bc
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Starting Final Cleanup Task
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Ending Final Cleanup Task | Checksum: 14dbbd0bc
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Starting Netlist Obfuscation Task
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Ending Netlist Obfuscation Task | Checksum: 14dbbd0bc
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1347.707 ; gain = 0.000
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INFO: [Common 17-83] Releasing license: Implementation
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30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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opt_design completed successfully
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing placer database...
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
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Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
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INFO: [IP_Flow 19-1839] IP Catalog is up to date.
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
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report_drc completed successfully
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Command: place_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Running DRC as a precondition to command place_design
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Placer Task
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INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
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Phase 1 Placer Initialization
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Phase 1.1 Placer Initialization Netlist Sorting
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fa6d7a79
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
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bouton_down_IBUF_inst (IBUF.O) is locked to IOB_X0Y1
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bouton_down_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1
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Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
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WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
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bouton_right_IBUF_inst (IBUF.O) is locked to IOB_X0Y36
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bouton_right_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
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Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12622357c
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.294 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 1.3 Build Placer Netlist Model
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Phase 1.3 Build Placer Netlist Model | Checksum: 1b3b55d5e
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.354 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 1.4 Constrain Clocks/Macros
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Phase 1.4 Constrain Clocks/Macros | Checksum: 1b3b55d5e
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.356 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 1 Placer Initialization | Checksum: 1b3b55d5e
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.356 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 2 Global Placement
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Phase 2.1 Floorplanning
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Phase 2.1 Floorplanning | Checksum: 1f34e0130
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.387 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 2.2 Physical Synthesis In Placer
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INFO: [Physopt 32-65] No nets found for high-fanout optimization.
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INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
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INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
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INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
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INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
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INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
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INFO: [Physopt 32-949] No candidate nets found for HD net replication
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INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Summary of Physical Synthesis Optimizations
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============================================
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----------------------------------------------------------------------------------------------------------------------------------------
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| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
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----------------------------------------------------------------------------------------------------------------------------------------
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| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
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| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
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| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
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| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
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| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
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| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
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----------------------------------------------------------------------------------------------------------------------------------------
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Phase 2.2 Physical Synthesis In Placer | Checksum: 1f822ab4a
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.899 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 2 Global Placement | Checksum: 17fde1b87
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.910 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 3 Detail Placement
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Phase 3.1 Commit Multi Column Macros
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Phase 3.1 Commit Multi Column Macros | Checksum: 17fde1b87
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.911 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 3.2 Commit Most Macros & LUTRAMs
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Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 258919723
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.945 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 3.3 Area Swap Optimization
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Phase 3.3 Area Swap Optimization | Checksum: 1af65d909
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.947 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 3.4 Pipeline Register Optimization
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Phase 3.4 Pipeline Register Optimization | Checksum: 245deb5d9
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.948 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 3.5 Small Shape Detail Placement
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Phase 3.5 Small Shape Detail Placement | Checksum: 1dab8f54b
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 3.6 Re-assign LUT pins
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Phase 3.6 Re-assign LUT pins | Checksum: 1e1eee966
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 3.7 Pipeline Register Optimization
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Phase 3.7 Pipeline Register Optimization | Checksum: f76e0896
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 3 Detail Placement | Checksum: f76e0896
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 4 Post Placement Optimization and Clean-Up
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Phase 4.1 Post Commit Optimization
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Phase 4.1.1 Post Placement Optimization
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Post Placement Optimization Initialization | Checksum: 13e7bd2c2
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Phase 4.1.1.1 BUFG Insertion
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INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
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Phase 4.1.1.1 BUFG Insertion | Checksum: 13e7bd2c2
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
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INFO: [Place 30-746] Post Placement Timing Summary WNS=35.645. For the most accurate timing information please run report_timing.
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Phase 4.1.1 Post Placement Optimization | Checksum: 15c183492
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 4.1 Post Commit Optimization | Checksum: 15c183492
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 4.2 Post Placement Cleanup
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Phase 4.2 Post Placement Cleanup | Checksum: 15c183492
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 4.3 Placer Reporting
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Phase 4.3 Placer Reporting | Checksum: 15c183492
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 4.4 Final Placement Cleanup
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 4.4 Final Placement Cleanup | Checksum: 17d5ce04d
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Phase 4 Post Placement Optimization and Clean-Up | Checksum: 17d5ce04d
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Ending Placer Task | Checksum: d443f812
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000
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INFO: [Common 17-83] Releasing license: Implementation
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57 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
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place_design completed successfully
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing placer database...
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
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report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1347.707 ; gain = 0.000
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INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
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INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
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report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1347.707 ; gain = 0.000
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Command: route_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
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Running DRC as a precondition to command route_design
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INFO: [DRC 23-27] Running DRC with 2 threads
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WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG.
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Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
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This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
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bouton_down_IBUF_inst (IBUF.O) is locked to IOB_X0Y1
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bouton_down_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1
|
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WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG.
|
|
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
|
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This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
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bouton_right_IBUF_inst (IBUF.O) is locked to IOB_X0Y36
|
|
bouton_right_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
|
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 2 Warnings
|
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Routing Task
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INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
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|
Checksum: PlaceDB: 52480e80 ConstDB: 0 ShapeSum: 81fbe992 RouteDB: 0
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Phase 1 Build RT Design
|
|
Phase 1 Build RT Design | Checksum: fee31c87
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Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1413.883 ; gain = 66.176
|
|
Post Restoration Checksum: NetGraph: e323ff66 NumContArr: 1bbf1d21 Constraints: 0 Timing: 0
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Phase 2 Router Initialization
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|
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Phase 2.1 Create Timer
|
|
Phase 2.1 Create Timer | Checksum: fee31c87
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Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1444.188 ; gain = 96.480
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|
|
Phase 2.2 Fix Topology Constraints
|
|
Phase 2.2 Fix Topology Constraints | Checksum: fee31c87
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|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1450.230 ; gain = 102.523
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|
|
Phase 2.3 Pre Route Cleanup
|
|
Phase 2.3 Pre Route Cleanup | Checksum: fee31c87
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|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1450.230 ; gain = 102.523
|
|
Number of Nodes with overlaps = 0
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|
|
|
Phase 2.4 Update Timing
|
|
Phase 2.4 Update Timing | Checksum: 1441c14dd
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|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1454.770 ; gain = 107.062
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.769 | TNS=0.000 | WHS=-0.258 | THS=-3.023 |
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|
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Phase 2 Router Initialization | Checksum: 173a347ed
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|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1454.770 ; gain = 107.062
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|
|
Phase 3 Initial Routing
|
|
Phase 3 Initial Routing | Checksum: 205eb8b74
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|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
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|
|
Phase 4 Rip-up And Reroute
|
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|
|
Phase 4.1 Global Iteration 0
|
|
Number of Nodes with overlaps = 17
|
|
Number of Nodes with overlaps = 0
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.132 | TNS=0.000 | WHS=N/A | THS=N/A |
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|
Phase 4.1 Global Iteration 0 | Checksum: 2843d0f71
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|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
|
|
Phase 4 Rip-up And Reroute | Checksum: 2843d0f71
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|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
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|
Phase 5 Delay and Skew Optimization
|
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|
|
Phase 5.1 Delay CleanUp
|
|
Phase 5.1 Delay CleanUp | Checksum: 2843d0f71
|
|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
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|
|
|
Phase 5.2 Clock Skew Optimization
|
|
Phase 5.2 Clock Skew Optimization | Checksum: 2843d0f71
|
|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
|
|
Phase 5 Delay and Skew Optimization | Checksum: 2843d0f71
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|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
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|
|
Phase 6 Post Hold Fix
|
|
|
|
Phase 6.1 Hold Fix Iter
|
|
|
|
Phase 6.1.1 Update Timing
|
|
Phase 6.1.1 Update Timing | Checksum: 1adede088
|
|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.132 | TNS=0.000 | WHS=0.069 | THS=0.000 |
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|
|
|
Phase 6.1 Hold Fix Iter | Checksum: 1adede088
|
|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
|
|
Phase 6 Post Hold Fix | Checksum: 1adede088
|
|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
|
|
|
|
Phase 7 Route finalize
|
|
|
|
Router Utilization Summary
|
|
Global Vertical Routing Utilization = 0.0615146 %
|
|
Global Horizontal Routing Utilization = 0.0558364 %
|
|
Routable Net Status*
|
|
*Does not include unroutable nets such as driverless and loadless.
|
|
Run report_route_status for detailed report.
|
|
Number of Failed Nets = 0
|
|
Number of Unrouted Nets = 0
|
|
Number of Partially Routed Nets = 0
|
|
Number of Node Overlaps = 0
|
|
|
|
Phase 7 Route finalize | Checksum: 2005f65b4
|
|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789
|
|
|
|
Phase 8 Verifying routed nets
|
|
|
|
Verification completed successfully
|
|
Phase 8 Verifying routed nets | Checksum: 2005f65b4
|
|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.543 ; gain = 108.836
|
|
|
|
Phase 9 Depositing Routes
|
|
Phase 9 Depositing Routes | Checksum: 18ba5fe80
|
|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.543 ; gain = 108.836
|
|
|
|
Phase 10 Post Router Timing
|
|
INFO: [Route 35-57] Estimated Timing Summary | WNS=35.132 | TNS=0.000 | WHS=0.069 | THS=0.000 |
|
|
|
|
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
|
Phase 10 Post Router Timing | Checksum: 18ba5fe80
|
|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.543 ; gain = 108.836
|
|
INFO: [Route 35-16] Router Completed Successfully
|
|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.543 ; gain = 108.836
|
|
|
|
Routing Is Done.
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|
74 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
route_design completed successfully
|
|
route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1456.543 ; gain = 108.836
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1456.543 ; gain = 0.000
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|
Writing placer database...
|
|
Writing XDEF routing.
|
|
Writing XDEF routing logical nets.
|
|
Writing XDEF routing special nets.
|
|
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1456.957 ; gain = 0.414
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1456.957 ; gain = 0.000
|
|
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
|
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
|
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
|
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
|
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
|
report_drc completed successfully
|
|
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
|
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
INFO: [DRC 23-133] Running Methodology with 2 threads
|
|
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
|
report_methodology completed successfully
|
|
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
|
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
Running Vector-less Activity Propagation...
|
|
|
|
Finished Running Vector-less Activity Propagation
|
|
86 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
report_power completed successfully
|
|
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
|
|
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
|
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
|
|
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
|
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
|
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
|
INFO: [Common 17-206] Exiting Vivado at Tue Nov 23 10:09:12 2021...
|