183 lines
14 KiB
Plaintext
183 lines
14 KiB
Plaintext
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
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| Date : Tue Dec 7 12:43:48 2021
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| Host : irb121-02-w running 64-bit major release (build 9200)
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| Command : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
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| Design : VGA_top
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| Device : 7z010-clg400
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| Speed File : -1 PRODUCTION 1.11 2014-09-11
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Clock Utilization Report
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Table of Contents
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-----------------
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1. Clock Primitive Utilization
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2. Global Clock Resources
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3. Global Clock Source Details
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4. Clock Regions: Key Resource Utilization
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5. Clock Regions : Global Clock Summary
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6. Device Cell Placement Summary for Global Clock g0
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7. Device Cell Placement Summary for Global Clock g1
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8. Clock Region Cell Placement per Global Clock: Region X1Y0
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9. Clock Region Cell Placement per Global Clock: Region X1Y1
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1. Clock Primitive Utilization
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------------------------------
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+----------+------+-----------+-----+--------------+--------+
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| Type | Used | Available | LOC | Clock Region | Pblock |
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+----------+------+-----------+-----+--------------+--------+
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| BUFGCTRL | 2 | 32 | 0 | 0 | 0 |
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| BUFH | 0 | 48 | 0 | 0 | 0 |
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| BUFIO | 0 | 8 | 0 | 0 | 0 |
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| BUFMR | 0 | 4 | 0 | 0 | 0 |
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| BUFR | 0 | 8 | 0 | 0 | 0 |
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| MMCM | 1 | 2 | 0 | 0 | 0 |
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| PLL | 0 | 2 | 0 | 0 | 0 |
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+----------+------+-----------+-----+--------------+--------+
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2. Global Clock Resources
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-------------------------
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+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+----------+-----------------------+--------------------------------+
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| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
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+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+----------+-----------------------+--------------------------------+
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| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 2 | 21 | 0 | 40.000 | Multiple | U0/inst/clkout1_buf/O | U0/inst/clk_out1 |
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| g1 | src0 | BUFG/O | None | BUFGCTRL_X0Y17 | n/a | 1 | 1 | 0 | 40.000 | Multiple | U0/inst/clkf_buf/O | U0/inst/clkfbout_buf_clk_wiz_1 |
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+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+----------+-----------------------+--------------------------------+
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* Clock Loads column represents the clock pin loads (pin count)
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** Non-Clock Loads column represents the non-clock pin loads (pin count)
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3. Global Clock Source Details
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------------------------------
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+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------+----------------------------+
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| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
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+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------+----------------------------+
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| src0 | g0 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X0Y1 | X1Y1 | 1 | 0 | 40.000 | Multiple | U0/inst/mmcm_adv_inst/CLKOUT0 | U0/inst/clk_out1_clk_wiz_1 |
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| src0 | g1 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X0Y1 | X1Y1 | 1 | 0 | 40.000 | Multiple | U0/inst/mmcm_adv_inst/CLKFBOUT | U0/inst/clkfbout_clk_wiz_1 |
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+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------+----------------------------+
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* Clock Loads column represents the clock pin loads (pin count)
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** Non-Clock Loads column represents the non-clock pin loads (pin count)
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4. Clock Regions: Key Resource Utilization
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------------------------------------------
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+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
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| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
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+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
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+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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| X0Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
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| X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3 | 1100 | 1 | 350 | 0 | 40 | 0 | 20 | 0 | 20 |
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| X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
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| X1Y1 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 18 | 1100 | 3 | 350 | 0 | 40 | 0 | 20 | 0 | 20 |
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+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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* Global Clock column represents track count; while other columns represents cell counts
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5. Clock Regions : Global Clock Summary
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---------------------------------------
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All Modules
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+----+----+----+
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| | X0 | X1 |
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+----+----+----+
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| Y1 | 0 | 2 |
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| Y0 | 0 | 1 |
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+----+----+----+
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6. Device Cell Placement Summary for Global Clock g0
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----------------------------------------------------
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+-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+------------------+
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| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
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+-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+------------------+
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| g0 | BUFG/O | n/a | Multiple | 40.000 | {0.000 20.000} | 21 | 0 | 0 | 0 | U0/inst/clk_out1 |
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+-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+------------------+
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* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources
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** IO Loads column represents load cell count of IO types
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*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
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**** GT Loads column represents load cell count of GT types
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+----+----+-----+
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| | X0 | X1 |
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+----+----+-----+
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| Y1 | 0 | 18 |
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| Y0 | 0 | 3 |
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+----+----+-----+
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7. Device Cell Placement Summary for Global Clock g1
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----------------------------------------------------
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+-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
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| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
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+-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
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| g1 | BUFG/O | n/a | Multiple | 40.000 | {0.000 20.000} | 0 | 0 | 1 | 0 | U0/inst/clkfbout_buf_clk_wiz_1 |
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+-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
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* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources
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** IO Loads column represents load cell count of IO types
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*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
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**** GT Loads column represents load cell count of GT types
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+----+----+----+
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| | X0 | X1 |
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+----+----+----+
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| Y1 | 0 | 1 |
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| Y0 | 0 | 0 |
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+----+----+----+
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8. Clock Region Cell Placement per Global Clock: Region X1Y0
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------------------------------------------------------------
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+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------+
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| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
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+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------+
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| g0 | n/a | BUFG/O | None | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | U0/inst/clk_out1 |
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+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------+
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* Clock Loads column represents the clock pin loads (pin count)
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** Non-Clock Loads column represents the non-clock pin loads (pin count)
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*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
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9. Clock Region Cell Placement per Global Clock: Region X1Y1
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------------------------------------------------------------
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+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+
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| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
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+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+
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| g0 | n/a | BUFG/O | None | 18 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | U0/inst/clk_out1 |
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| g1 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | U0/inst/clkfbout_buf_clk_wiz_1 |
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+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+
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* Clock Loads column represents the clock pin loads (pin count)
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** Non-Clock Loads column represents the non-clock pin loads (pin count)
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*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
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# Location of BUFG Primitives
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set_property LOC BUFGCTRL_X0Y17 [get_cells U0/inst/clkf_buf]
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set_property LOC BUFGCTRL_X0Y16 [get_cells U0/inst/clkout1_buf]
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# Location of IO Primitives which is load of clock spine
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# Location of clock ports
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set_property LOC IOB_X0Y78 [get_ports H125MHz]
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# Clock net "U0/inst/clk_out1" driven by instance "U0/inst/clkout1_buf" located at site "BUFGCTRL_X0Y16"
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#startgroup
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create_pblock {CLKAG_U0/inst/clk_out1}
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add_cells_to_pblock [get_pblocks {CLKAG_U0/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="U0/inst/clk_out1"}]]]
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resize_pblock [get_pblocks {CLKAG_U0/inst/clk_out1}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
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#endgroup
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