586 lines
31 KiB
Plaintext
586 lines
31 KiB
Plaintext
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*** Running vivado
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with args -log VGA_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
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****** Vivado v2018.3 (64-bit)
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**** SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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**** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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source VGA_top.tcl -notrace
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Command: link_design -top VGA_top -part xc7z010clg400-1
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Design is defaulting to srcset: sources_1
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Design is defaulting to constrset: constrs_1
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INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
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INFO: [Netlist 29-17] Analyzing 35 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
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INFO: [Project 1-479] Netlist was created with Vivado 2018.3
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INFO: [Device 21-403] Loading part xc7z010clg400-1
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
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Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
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Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
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INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
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INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
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get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1248.586 ; gain = 558.375
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Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
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Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
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Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1248.586 ; gain = 0.000
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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link_design completed successfully
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link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1248.586 ; gain = 885.598
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Command: opt_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
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Running DRC as a precondition to command opt_design
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Starting DRC Task
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Project 1-461] DRC finished with 0 Errors
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INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.499 . Memory (MB): peak = 1248.586 ; gain = 0.000
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Starting Cache Timing Information Task
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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INFO: [Timing 38-2] Deriving generated clocks
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Ending Cache Timing Information Task | Checksum: 20ae1d4cd
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1265.152 ; gain = 16.566
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Starting Logic Optimization Task
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Phase 1 Retarget
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Opt 31-49] Retargeted 0 cell(s).
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Phase 1 Retarget | Checksum: ddde5939
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1351.098 ; gain = 0.000
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INFO: [Opt 31-389] Phase Retarget created 4 cells and removed 4 cells
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INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
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Phase 2 Constant propagation
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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Phase 2 Constant propagation | Checksum: ddde5939
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1351.098 ; gain = 0.000
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INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
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Phase 3 Sweep
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Phase 3 Sweep | Checksum: fec5e707
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1351.098 ; gain = 0.000
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INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
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Phase 4 BUFG optimization
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INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
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INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
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Phase 4 BUFG optimization | Checksum: 137e6b9d1
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1351.098 ; gain = 0.000
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INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
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Phase 5 Shift Register Optimization
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Phase 5 Shift Register Optimization | Checksum: 12c29fba6
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1351.098 ; gain = 0.000
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INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
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Phase 6 Post Processing Netlist
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Phase 6 Post Processing Netlist | Checksum: 10c49128f
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1351.098 ; gain = 0.000
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INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
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Opt_design Change Summary
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=========================
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-------------------------------------------------------------------------------------------------------------------------
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| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
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-------------------------------------------------------------------------------------------------------------------------
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| Retarget | 4 | 4 | 1 |
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| Constant propagation | 0 | 0 | 0 |
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| Sweep | 0 | 0 | 0 |
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| BUFG optimization | 0 | 0 | 0 |
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| Shift Register Optimization | 0 | 0 | 0 |
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| Post Processing Netlist | 0 | 0 | 0 |
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-------------------------------------------------------------------------------------------------------------------------
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Starting Connectivity Check Task
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Ending Logic Optimization Task | Checksum: e54fefee
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Starting Power Optimization Task
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INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
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Ending Power Optimization Task | Checksum: e54fefee
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Starting Final Cleanup Task
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Ending Final Cleanup Task | Checksum: e54fefee
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Starting Netlist Obfuscation Task
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Ending Netlist Obfuscation Task | Checksum: e54fefee
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
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INFO: [Common 17-83] Releasing license: Implementation
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30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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opt_design completed successfully
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing placer database...
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
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Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
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INFO: [IP_Flow 19-1839] IP Catalog is up to date.
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
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report_drc completed successfully
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Command: place_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Running DRC as a precondition to command place_design
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Placer Task
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INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
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Phase 1 Placer Initialization
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Phase 1.1 Placer Initialization Netlist Sorting
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 4ed236ad
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1a1c16c9c
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.262 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 1.3 Build Placer Netlist Model
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Phase 1.3 Build Placer Netlist Model | Checksum: 2939760d0
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.351 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 1.4 Constrain Clocks/Macros
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Phase 1.4 Constrain Clocks/Macros | Checksum: 2939760d0
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.353 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 1 Placer Initialization | Checksum: 2939760d0
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.353 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 2 Global Placement
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Phase 2.1 Floorplanning
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Phase 2.1 Floorplanning | Checksum: 28231f14d
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.397 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 2.2 Physical Synthesis In Placer
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INFO: [Physopt 32-65] No nets found for high-fanout optimization.
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INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
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INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
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INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
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INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
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INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
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INFO: [Physopt 32-949] No candidate nets found for HD net replication
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INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Summary of Physical Synthesis Optimizations
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============================================
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----------------------------------------------------------------------------------------------------------------------------------------
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| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
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----------------------------------------------------------------------------------------------------------------------------------------
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| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
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| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
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| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
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| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
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| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
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| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
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----------------------------------------------------------------------------------------------------------------------------------------
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Phase 2.2 Physical Synthesis In Placer | Checksum: 22348ffd6
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 2 Global Placement | Checksum: 2038a7242
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 3 Detail Placement
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Phase 3.1 Commit Multi Column Macros
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Phase 3.1 Commit Multi Column Macros | Checksum: 2038a7242
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 3.2 Commit Most Macros & LUTRAMs
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Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2c58c3354
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 3.3 Area Swap Optimization
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Phase 3.3 Area Swap Optimization | Checksum: 279aeb7b4
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 3.4 Pipeline Register Optimization
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Phase 3.4 Pipeline Register Optimization | Checksum: 279aeb7b4
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 3.5 Small Shape Detail Placement
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Phase 3.5 Small Shape Detail Placement | Checksum: 1e0aaeea1
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 3.6 Re-assign LUT pins
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Phase 3.6 Re-assign LUT pins | Checksum: 2d338840d
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 3.7 Pipeline Register Optimization
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Phase 3.7 Pipeline Register Optimization | Checksum: 2d338840d
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 3 Detail Placement | Checksum: 2d338840d
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 4 Post Placement Optimization and Clean-Up
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Phase 4.1 Post Commit Optimization
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Phase 4.1.1 Post Placement Optimization
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Post Placement Optimization Initialization | Checksum: 15c68dcd4
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Phase 4.1.1.1 BUFG Insertion
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INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
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Phase 4.1.1.1 BUFG Insertion | Checksum: 15c68dcd4
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
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INFO: [Place 30-746] Post Placement Timing Summary WNS=35.245. For the most accurate timing information please run report_timing.
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Phase 4.1.1 Post Placement Optimization | Checksum: 142e419cd
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 4.1 Post Commit Optimization | Checksum: 142e419cd
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 4.2 Post Placement Cleanup
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Phase 4.2 Post Placement Cleanup | Checksum: 142e419cd
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 4.3 Placer Reporting
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Phase 4.3 Placer Reporting | Checksum: 142e419cd
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 4.4 Final Placement Cleanup
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 4.4 Final Placement Cleanup | Checksum: 20695260e
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Phase 4 Post Placement Optimization and Clean-Up | Checksum: 20695260e
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Ending Placer Task | Checksum: 1f2b3c1b8
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000
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INFO: [Common 17-83] Releasing license: Implementation
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57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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place_design completed successfully
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing placer database...
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1351.098 ; gain = 0.000
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
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|
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
|
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
|
|
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
|
|
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000
|
|
Command: route_design
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
|
Running DRC as a precondition to command route_design
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
|
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
|
|
|
|
|
Starting Routing Task
|
|
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
|
Checksum: PlaceDB: f9e7c0c6 ConstDB: 0 ShapeSum: f8cc00f2 RouteDB: 0
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|
|
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Phase 1 Build RT Design
|
|
Phase 1 Build RT Design | Checksum: 9a64d846
|
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|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1417.348 ; gain = 66.250
|
|
Post Restoration Checksum: NetGraph: 7c5b36de NumContArr: 1e09a168 Constraints: 0 Timing: 0
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Phase 2 Router Initialization
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|
|
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Phase 2.1 Create Timer
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Phase 2.1 Create Timer | Checksum: 9a64d846
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Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1449.676 ; gain = 98.578
|
|
|
|
Phase 2.2 Fix Topology Constraints
|
|
Phase 2.2 Fix Topology Constraints | Checksum: 9a64d846
|
|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1455.699 ; gain = 104.602
|
|
|
|
Phase 2.3 Pre Route Cleanup
|
|
Phase 2.3 Pre Route Cleanup | Checksum: 9a64d846
|
|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1455.699 ; gain = 104.602
|
|
Number of Nodes with overlaps = 0
|
|
|
|
Phase 2.4 Update Timing
|
|
Phase 2.4 Update Timing | Checksum: 82bae049
|
|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.391 | TNS=0.000 | WHS=-0.239 | THS=-2.915 |
|
|
|
|
Phase 2 Router Initialization | Checksum: cf693307
|
|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
|
|
|
Phase 3 Initial Routing
|
|
Phase 3 Initial Routing | Checksum: 16fee48da
|
|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
|
|
|
Phase 4 Rip-up And Reroute
|
|
|
|
Phase 4.1 Global Iteration 0
|
|
Number of Nodes with overlaps = 36
|
|
Number of Nodes with overlaps = 0
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=33.088 | TNS=0.000 | WHS=N/A | THS=N/A |
|
|
|
|
Phase 4.1 Global Iteration 0 | Checksum: 1c93f85f6
|
|
|
|
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
|
Phase 4 Rip-up And Reroute | Checksum: 1c93f85f6
|
|
|
|
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
|
|
|
Phase 5 Delay and Skew Optimization
|
|
|
|
Phase 5.1 Delay CleanUp
|
|
Phase 5.1 Delay CleanUp | Checksum: 1c93f85f6
|
|
|
|
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
|
|
|
Phase 5.2 Clock Skew Optimization
|
|
Phase 5.2 Clock Skew Optimization | Checksum: 1c93f85f6
|
|
|
|
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
|
Phase 5 Delay and Skew Optimization | Checksum: 1c93f85f6
|
|
|
|
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
|
|
|
Phase 6 Post Hold Fix
|
|
|
|
Phase 6.1 Hold Fix Iter
|
|
|
|
Phase 6.1.1 Update Timing
|
|
Phase 6.1.1 Update Timing | Checksum: 144941f51
|
|
|
|
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=33.241 | TNS=0.000 | WHS=0.083 | THS=0.000 |
|
|
|
|
Phase 6.1 Hold Fix Iter | Checksum: 144941f51
|
|
|
|
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
|
Phase 6 Post Hold Fix | Checksum: 144941f51
|
|
|
|
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
|
|
|
Phase 7 Route finalize
|
|
|
|
Router Utilization Summary
|
|
Global Vertical Routing Utilization = 0.0881194 %
|
|
Global Horizontal Routing Utilization = 0.100414 %
|
|
Routable Net Status*
|
|
*Does not include unroutable nets such as driverless and loadless.
|
|
Run report_route_status for detailed report.
|
|
Number of Failed Nets = 0
|
|
Number of Unrouted Nets = 0
|
|
Number of Partially Routed Nets = 0
|
|
Number of Node Overlaps = 0
|
|
|
|
Phase 7 Route finalize | Checksum: 19cea99c1
|
|
|
|
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348
|
|
|
|
Phase 8 Verifying routed nets
|
|
|
|
Verification completed successfully
|
|
Phase 8 Verifying routed nets | Checksum: 19cea99c1
|
|
|
|
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
|
|
|
Phase 9 Depositing Routes
|
|
Phase 9 Depositing Routes | Checksum: 17f26a4e0
|
|
|
|
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
|
|
|
Phase 10 Post Router Timing
|
|
INFO: [Route 35-57] Estimated Timing Summary | WNS=33.241 | TNS=0.000 | WHS=0.083 | THS=0.000 |
|
|
|
|
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
|
Phase 10 Post Router Timing | Checksum: 17f26a4e0
|
|
|
|
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
|
INFO: [Route 35-16] Router Completed Successfully
|
|
|
|
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
|
|
|
Routing Is Done.
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|
74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
route_design completed successfully
|
|
route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 1461.477 ; gain = 110.379
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.477 ; gain = 0.000
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|
Writing placer database...
|
|
Writing XDEF routing.
|
|
Writing XDEF routing logical nets.
|
|
Writing XDEF routing special nets.
|
|
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1461.910 ; gain = 0.434
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.910 ; gain = 0.000
|
|
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
|
|
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
|
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
|
|
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
|
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
|
|
report_drc completed successfully
|
|
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
|
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
INFO: [DRC 23-133] Running Methodology with 2 threads
|
|
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
|
|
report_methodology completed successfully
|
|
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
|
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
Running Vector-less Activity Propagation...
|
|
|
|
Finished Running Vector-less Activity Propagation
|
|
86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
report_power completed successfully
|
|
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
|
|
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
|
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
|
|
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
|
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
|
|
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
|
INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:43:48 2021...
|
|
|
|
*** Running vivado
|
|
with args -log VGA_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
|
|
|
|
|
|
****** Vivado v2018.3 (64-bit)
|
|
**** SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
|
**** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source VGA_top.tcl -notrace
|
|
Command: open_checkpoint VGA_top_routed.dcp
|
|
|
|
Starting open_checkpoint Task
|
|
|
|
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 250.652 ; gain = 0.000
|
|
INFO: [Netlist 29-17] Analyzing 35 Unisim elements for replacement
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
|
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|
INFO: [Timing 38-478] Restoring timing data from binary archive.
|
|
INFO: [Timing 38-479] Binary timing data restore complete.
|
|
INFO: [Project 1-856] Restoring constraints from binary archive.
|
|
INFO: [Project 1-853] Binary constraint restore complete.
|
|
Reading XDEF placement.
|
|
Reading placer database...
|
|
Reading XDEF routing.
|
|
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.095 . Memory (MB): peak = 1208.145 ; gain = 0.000
|
|
Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
|
|
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.095 . Memory (MB): peak = 1208.145 ; gain = 0.000
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1208.145 ; gain = 0.000
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
No Unisim elements were transformed.
|
|
|
|
INFO: [Project 1-604] Checkpoint was created with Vivado v2018.3 (64-bit) build 2405991
|
|
open_checkpoint: Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 1208.145 ; gain = 957.492
|
|
Command: write_bitstream -force VGA_top.bit
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
|
Running DRC as a precondition to command write_bitstream
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'.
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
|
WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
|
|
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
|
|
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
|
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
|
|
Loading data files...
|
|
Loading site data...
|
|
Loading route data...
|
|
Processing options...
|
|
Creating bitmap...
|
|
Creating bitstream...
|
|
Writing bitstream ./VGA_top.bit...
|
|
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
|
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|
22 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
write_bitstream completed successfully
|
|
write_bitstream: Time (s): cpu = 00:00:10 ; elapsed = 00:00:28 . Memory (MB): peak = 1679.344 ; gain = 471.199
|
|
INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:44:53 2021...
|