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snake-vhdl/projet-vga.runs/impl_1/usage_statistics_webtalk.html
Yann Salmon f3322c1e52 seance-07-12-2021
2021-12-07 21:46:03 +01:00

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<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
<TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2405991</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Tue Dec 7 12:44:52 2021</TD>
<TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2018.3 (64-bit)</TD>
<TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>5587c47a25864f30a941d919a4588f42</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>43</TD>
<TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>5c5083d208095dd793a4532428ca92e6</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>5c5083d208095dd793a4532428ca92e6</TD>
<TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7z010</TD>
<TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>zynq</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>clg400</TD>
<TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i7-10700 CPU @ 2.90GHz</TD>
<TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2904 MHz</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Microsoft Windows 8 or later , 64-bit</TD>
<TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release (build 9200)</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>16.000 GB</TD>
<TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'> <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>gui_handlers</B></TD></TR>
<TR ALIGN='LEFT'> <TD>abstractcombinedpanel_add_element=9</TD>
<TD>abstractcombinedpanel_remove_selected_elements=2</TD>
<TD>abstractfileview_close=1</TD>
<TD>basedialog_cancel=45</TD>
</TR><TR ALIGN='LEFT'> <TD>basedialog_close=1</TD>
<TD>basedialog_no=1</TD>
<TD>basedialog_ok=396</TD>
<TD>basedialog_yes=2</TD>
</TR><TR ALIGN='LEFT'> <TD>constraintschooserpanel_add_files=1</TD>
<TD>coretreetablepanel_core_tree_table=18</TD>
<TD>createsrcfiledialog_file_name=5</TD>
<TD>definemodulesdialog_define_modules_and_specify_io_ports=95</TD>
</TR><TR ALIGN='LEFT'> <TD>filesetpanel_file_set_panel_tree=157</TD>
<TD>flownavigatortreepanel_flow_navigator_tree=206</TD>
<TD>fpgachooser_fpga_table=1</TD>
<TD>gettingstartedview_create_new_project=1</TD>
</TR><TR ALIGN='LEFT'> <TD>hcodeeditor_blank_operations=17</TD>
<TD>hcodeeditor_close=1</TD>
<TD>hcodeeditor_commands_to_fold_text=2</TD>
<TD>hcodeeditor_diff_with=8</TD>
</TR><TR ALIGN='LEFT'> <TD>hcodeeditor_search_text_combo_box=15</TD>
<TD>hinputhandler_indent_selection=1</TD>
<TD>hinputhandler_toggle_line_comments=37</TD>
<TD>hinputhandler_unindent_selection=2</TD>
</TR><TR ALIGN='LEFT'> <TD>hpopuptitle_close=1</TD>
<TD>logmonitor_monitor=3</TD>
<TD>msgtreepanel_manage_suppression=1</TD>
<TD>msgtreepanel_message_view_tree=79</TD>
</TR><TR ALIGN='LEFT'> <TD>msgview_clear_messages_resulting_from_user_executed=1</TD>
<TD>msgview_critical_warnings=2</TD>
<TD>msgview_error_messages=4</TD>
<TD>msgview_information_messages=3</TD>
</TR><TR ALIGN='LEFT'> <TD>msgview_warning_messages=9</TD>
<TD>numjobschooser_number_of_jobs=2</TD>
<TD>pacommandnames_auto_connect_target=16</TD>
<TD>pacommandnames_auto_update_hier=11</TD>
</TR><TR ALIGN='LEFT'> <TD>pacommandnames_goto_implemented_design=1</TD>
<TD>pacommandnames_goto_netlist_design=1</TD>
<TD>pacommandnames_log_window=1</TD>
<TD>pacommandnames_open_hardware_manager=2</TD>
</TR><TR ALIGN='LEFT'> <TD>pacommandnames_recustomize_core=1</TD>
<TD>pacommandnames_run_bitgen=42</TD>
<TD>pacommandnames_run_implementation=8</TD>
<TD>paviews_code=5</TD>
</TR><TR ALIGN='LEFT'> <TD>paviews_device=3</TD>
<TD>paviews_ip_catalog=1</TD>
<TD>paviews_project_summary=21</TD>
<TD>paviews_schematic=9</TD>
</TR><TR ALIGN='LEFT'> <TD>programdebugtab_refresh_device=1</TD>
<TD>programfpgadialog_program=45</TD>
<TD>progressdialog_background=4</TD>
<TD>progressdialog_cancel=5</TD>
</TR><TR ALIGN='LEFT'> <TD>projectnamechooser_project_name=1</TD>
<TD>projecttab_reload=6</TD>
<TD>rdicommands_delete=4</TD>
<TD>rungadget_show_warning_and_error_messages_in_messages=2</TD>
</TR><TR ALIGN='LEFT'> <TD>saveprojectutils_dont_save=8</TD>
<TD>saveprojectutils_save=5</TD>
<TD>schematicview_previous=10</TD>
<TD>simpleoutputproductdialog_generate_output_products_immediately=3</TD>
</TR><TR ALIGN='LEFT'> <TD>srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1</TD>
<TD>srcchooserpanel_add_or_create_source_file=1</TD>
<TD>srcchooserpanel_create_file=6</TD>
<TD>srcmenu_ip_documentation=5</TD>
</TR><TR ALIGN='LEFT'> <TD>srcmenu_ip_hierarchy=8</TD>
<TD>stalerundialog_no=1</TD>
<TD>syntheticagettingstartedview_recent_projects=4</TD>
<TD>syntheticastatemonitor_cancel=5</TD>
</TR><TR ALIGN='LEFT'> <TD>taskbanner_close=16</TD>
</TR> </TABLE>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
<TR ALIGN='LEFT'> <TD>addsources=6</TD>
<TD>autoconnecttarget=16</TD>
<TD>coreview=3</TD>
<TD>customizecore=4</TD>
</TR><TR ALIGN='LEFT'> <TD>editdelete=4</TD>
<TD>editpaste=2</TD>
<TD>editundo=1</TD>
<TD>launchprogramfpga=45</TD>
</TR><TR ALIGN='LEFT'> <TD>newproject=1</TD>
<TD>openhardwaremanager=67</TD>
<TD>openrecenttarget=21</TD>
<TD>programdevice=45</TD>
</TR><TR ALIGN='LEFT'> <TD>recustomizecore=3</TD>
<TD>runbitgen=45</TD>
<TD>runimplementation=59</TD>
<TD>runschematic=7</TD>
</TR><TR ALIGN='LEFT'> <TD>runsynthesis=92</TD>
<TD>savefileproxyhandler=3</TD>
<TD>showview=24</TD>
<TD>viewtaskimplementation=8</TD>
</TR><TR ALIGN='LEFT'> <TD>viewtaskrtlanalysis=3</TD>
<TD>viewtasksynthesis=2</TD>
</TR> </TABLE>
</TR><TR ALIGN='LEFT'> <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
<TR ALIGN='LEFT'> <TD>guimode=5</TD>
</TR> </TABLE>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'> <TD>constraintsetcount=1</TD>
<TD>core_container=false</TD>
<TD>currentimplrun=impl_1</TD>
<TD>currentsynthesisrun=synth_1</TD>
</TR><TR ALIGN='LEFT'> <TD>default_library=xil_defaultlib</TD>
<TD>designmode=RTL</TD>
<TD>export_simulation_activehdl=2</TD>
<TD>export_simulation_ies=2</TD>
</TR><TR ALIGN='LEFT'> <TD>export_simulation_modelsim=2</TD>
<TD>export_simulation_questa=2</TD>
<TD>export_simulation_riviera=2</TD>
<TD>export_simulation_vcs=2</TD>
</TR><TR ALIGN='LEFT'> <TD>export_simulation_xsim=2</TD>
<TD>implstrategy=Vivado Implementation Defaults</TD>
<TD>launch_simulation_activehdl=0</TD>
<TD>launch_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'> <TD>launch_simulation_modelsim=0</TD>
<TD>launch_simulation_questa=0</TD>
<TD>launch_simulation_riviera=0</TD>
<TD>launch_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'> <TD>launch_simulation_xsim=0</TD>
<TD>simulator_language=VHDL</TD>
<TD>srcsetcount=8</TD>
<TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
</TR><TR ALIGN='LEFT'> <TD>target_language=VHDL</TD>
<TD>target_simulator=XSim</TD>
<TD>totalimplruns=1</TD>
<TD>totalsynthesisruns=1</TD>
</TR> </TABLE>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bufg=2</TD>
<TD>carry4=34</TD>
<TD>fdre=21</TD>
<TD>gnd=2</TD>
</TR><TR ALIGN='LEFT'> <TD>ibuf=1</TD>
<TD>lut1=4</TD>
<TD>lut2=28</TD>
<TD>lut3=7</TD>
</TR><TR ALIGN='LEFT'> <TD>lut4=62</TD>
<TD>lut5=47</TD>
<TD>lut6=65</TD>
<TD>mmcme2_adv=1</TD>
</TR><TR ALIGN='LEFT'> <TD>obuf=18</TD>
<TD>vcc=2</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bufg=2</TD>
<TD>carry4=34</TD>
<TD>fdre=21</TD>
<TD>gnd=2</TD>
</TR><TR ALIGN='LEFT'> <TD>ibuf=1</TD>
<TD>lut1=4</TD>
<TD>lut2=28</TD>
<TD>lut3=7</TD>
</TR><TR ALIGN='LEFT'> <TD>lut4=62</TD>
<TD>lut5=47</TD>
<TD>lut6=65</TD>
<TD>mmcme2_adv=1</TD>
</TR><TR ALIGN='LEFT'> <TD>obuf=18</TD>
<TD>vcc=2</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>ip_statistics</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clk_wiz_v6_0_2_0_0/1</B></TD></TR>
<TR ALIGN='LEFT'> <TD>clkin1_period=8.000</TD>
<TD>clkin2_period=10.000</TD>
<TD>clock_mgr_type=NA</TD>
<TD>component_name=clk_wiz_1</TD>
</TR><TR ALIGN='LEFT'> <TD>core_container=NA</TD>
<TD>enable_axi=0</TD>
<TD>feedback_source=FDBK_AUTO</TD>
<TD>feedback_type=SINGLE</TD>
</TR><TR ALIGN='LEFT'> <TD>iptotal=1</TD>
<TD>manual_override=false</TD>
<TD>num_out_clk=1</TD>
<TD>primitive=MMCM</TD>
</TR><TR ALIGN='LEFT'> <TD>use_dyn_phase_shift=false</TD>
<TD>use_dyn_reconfig=false</TD>
<TD>use_inclk_stopped=false</TD>
<TD>use_inclk_switchover=false</TD>
</TR><TR ALIGN='LEFT'> <TD>use_locked=false</TD>
<TD>use_max_i_jitter=false</TD>
<TD>use_min_o_jitter=false</TD>
<TD>use_phase_alignment=true</TD>
</TR><TR ALIGN='LEFT'> <TD>use_power_down=false</TD>
<TD>use_reset=false</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>-append=default::[not_specified]</TD>
<TD>-checks=default::[not_specified]</TD>
<TD>-fail_on=default::[not_specified]</TD>
<TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-format=default::[not_specified]</TD>
<TD>-internal=default::[not_specified]</TD>
<TD>-internal_only=default::[not_specified]</TD>
<TD>-messages=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-name=default::[not_specified]</TD>
<TD>-no_waivers=default::[not_specified]</TD>
<TD>-return_string=default::[not_specified]</TD>
<TD>-ruledecks=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-upgrade_cw=default::[not_specified]</TD>
<TD>-waived=default::[not_specified]</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'> <TD>zps7-1=1</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bufgctrl_available=32</TD>
<TD>bufgctrl_fixed=0</TD>
<TD>bufgctrl_used=2</TD>
<TD>bufgctrl_util_percentage=6.25</TD>
</TR><TR ALIGN='LEFT'> <TD>bufhce_available=48</TD>
<TD>bufhce_fixed=0</TD>
<TD>bufhce_used=0</TD>
<TD>bufhce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>bufio_available=8</TD>
<TD>bufio_fixed=0</TD>
<TD>bufio_used=0</TD>
<TD>bufio_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>bufmrce_available=4</TD>
<TD>bufmrce_fixed=0</TD>
<TD>bufmrce_used=0</TD>
<TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>bufr_available=8</TD>
<TD>bufr_fixed=0</TD>
<TD>bufr_used=0</TD>
<TD>bufr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>mmcme2_adv_available=2</TD>
<TD>mmcme2_adv_fixed=0</TD>
<TD>mmcme2_adv_used=1</TD>
<TD>mmcme2_adv_util_percentage=50.00</TD>
</TR><TR ALIGN='LEFT'> <TD>plle2_adv_available=2</TD>
<TD>plle2_adv_fixed=0</TD>
<TD>plle2_adv_used=0</TD>
<TD>plle2_adv_util_percentage=0.00</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'> <TD>dsps_available=80</TD>
<TD>dsps_fixed=0</TD>
<TD>dsps_used=0</TD>
<TD>dsps_util_percentage=0.00</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'> <TD>blvds_25=0</TD>
<TD>diff_hstl_i=0</TD>
<TD>diff_hstl_i_18=0</TD>
<TD>diff_hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'> <TD>diff_hstl_ii_18=0</TD>
<TD>diff_hsul_12=0</TD>
<TD>diff_mobile_ddr=0</TD>
<TD>diff_sstl135=0</TD>
</TR><TR ALIGN='LEFT'> <TD>diff_sstl135_r=0</TD>
<TD>diff_sstl15=0</TD>
<TD>diff_sstl15_r=0</TD>
<TD>diff_sstl18_i=0</TD>
</TR><TR ALIGN='LEFT'> <TD>diff_sstl18_ii=0</TD>
<TD>hstl_i=0</TD>
<TD>hstl_i_18=0</TD>
<TD>hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'> <TD>hstl_ii_18=0</TD>
<TD>hsul_12=0</TD>
<TD>lvcmos12=0</TD>
<TD>lvcmos15=0</TD>
</TR><TR ALIGN='LEFT'> <TD>lvcmos18=0</TD>
<TD>lvcmos25=0</TD>
<TD>lvcmos33=1</TD>
<TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'> <TD>lvttl=0</TD>
<TD>mini_lvds_25=0</TD>
<TD>mobile_ddr=0</TD>
<TD>pci33_3=0</TD>
</TR><TR ALIGN='LEFT'> <TD>ppds_25=0</TD>
<TD>rsds_25=0</TD>
<TD>sstl135=0</TD>
<TD>sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'> <TD>sstl15=0</TD>
<TD>sstl15_r=0</TD>
<TD>sstl18_i=0</TD>
<TD>sstl18_ii=0</TD>
</TR><TR ALIGN='LEFT'> <TD>tmds_33=0</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'> <TD>block_ram_tile_available=60</TD>
<TD>block_ram_tile_fixed=0</TD>
<TD>block_ram_tile_used=0</TD>
<TD>block_ram_tile_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>ramb18_available=120</TD>
<TD>ramb18_fixed=0</TD>
<TD>ramb18_used=0</TD>
<TD>ramb18_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>ramb36_fifo_available=60</TD>
<TD>ramb36_fifo_fixed=0</TD>
<TD>ramb36_fifo_used=0</TD>
<TD>ramb36_fifo_util_percentage=0.00</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bufg_functional_category=Clock</TD>
<TD>bufg_used=2</TD>
<TD>carry4_functional_category=CarryLogic</TD>
<TD>carry4_used=34</TD>
</TR><TR ALIGN='LEFT'> <TD>fdre_functional_category=Flop &amp; Latch</TD>
<TD>fdre_used=21</TD>
<TD>ibuf_functional_category=IO</TD>
<TD>ibuf_used=1</TD>
</TR><TR ALIGN='LEFT'> <TD>lut1_functional_category=LUT</TD>
<TD>lut1_used=4</TD>
<TD>lut2_functional_category=LUT</TD>
<TD>lut2_used=28</TD>
</TR><TR ALIGN='LEFT'> <TD>lut3_functional_category=LUT</TD>
<TD>lut3_used=7</TD>
<TD>lut4_functional_category=LUT</TD>
<TD>lut4_used=64</TD>
</TR><TR ALIGN='LEFT'> <TD>lut5_functional_category=LUT</TD>
<TD>lut5_used=47</TD>
<TD>lut6_functional_category=LUT</TD>
<TD>lut6_used=63</TD>
</TR><TR ALIGN='LEFT'> <TD>mmcme2_adv_functional_category=Clock</TD>
<TD>mmcme2_adv_used=1</TD>
<TD>obuf_functional_category=IO</TD>
<TD>obuf_used=18</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'> <TD>f7_muxes_available=8800</TD>
<TD>f7_muxes_fixed=0</TD>
<TD>f7_muxes_used=0</TD>
<TD>f7_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>f8_muxes_available=4400</TD>
<TD>f8_muxes_fixed=0</TD>
<TD>f8_muxes_used=0</TD>
<TD>f8_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_logic_available=17600</TD>
<TD>lut_as_logic_fixed=0</TD>
<TD>lut_as_logic_used=168</TD>
<TD>lut_as_logic_util_percentage=0.95</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_memory_available=6000</TD>
<TD>lut_as_memory_fixed=0</TD>
<TD>lut_as_memory_used=0</TD>
<TD>lut_as_memory_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>register_as_flip_flop_available=35200</TD>
<TD>register_as_flip_flop_fixed=0</TD>
<TD>register_as_flip_flop_used=21</TD>
<TD>register_as_flip_flop_util_percentage=0.06</TD>
</TR><TR ALIGN='LEFT'> <TD>register_as_latch_available=35200</TD>
<TD>register_as_latch_fixed=0</TD>
<TD>register_as_latch_used=0</TD>
<TD>register_as_latch_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>slice_luts_available=17600</TD>
<TD>slice_luts_fixed=0</TD>
<TD>slice_luts_used=168</TD>
<TD>slice_luts_util_percentage=0.95</TD>
</TR><TR ALIGN='LEFT'> <TD>slice_registers_available=35200</TD>
<TD>slice_registers_fixed=0</TD>
<TD>slice_registers_used=21</TD>
<TD>slice_registers_util_percentage=0.06</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_distributed_ram_fixed=0</TD>
<TD>lut_as_distributed_ram_used=0</TD>
<TD>lut_as_logic_available=17600</TD>
<TD>lut_as_logic_fixed=0</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_logic_used=168</TD>
<TD>lut_as_logic_util_percentage=0.95</TD>
<TD>lut_as_memory_available=6000</TD>
<TD>lut_as_memory_fixed=0</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_memory_used=0</TD>
<TD>lut_as_memory_util_percentage=0.00</TD>
<TD>lut_as_shift_register_fixed=0</TD>
<TD>lut_as_shift_register_used=0</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_in_front_of_the_register_is_unused_fixed=0</TD>
<TD>lut_in_front_of_the_register_is_unused_used=0</TD>
<TD>lut_in_front_of_the_register_is_used_fixed=0</TD>
<TD>lut_in_front_of_the_register_is_used_used=1</TD>
</TR><TR ALIGN='LEFT'> <TD>register_driven_from_outside_the_slice_fixed=1</TD>
<TD>register_driven_from_outside_the_slice_used=1</TD>
<TD>register_driven_from_within_the_slice_fixed=1</TD>
<TD>register_driven_from_within_the_slice_used=20</TD>
</TR><TR ALIGN='LEFT'> <TD>slice_available=4400</TD>
<TD>slice_fixed=0</TD>
<TD>slice_registers_available=35200</TD>
<TD>slice_registers_fixed=0</TD>
</TR><TR ALIGN='LEFT'> <TD>slice_registers_used=21</TD>
<TD>slice_registers_util_percentage=0.06</TD>
<TD>slice_used=61</TD>
<TD>slice_util_percentage=1.39</TD>
</TR><TR ALIGN='LEFT'> <TD>slicel_fixed=0</TD>
<TD>slicel_used=45</TD>
<TD>slicem_fixed=0</TD>
<TD>slicem_used=16</TD>
</TR><TR ALIGN='LEFT'> <TD>unique_control_sets_available=4400</TD>
<TD>unique_control_sets_fixed=4400</TD>
<TD>unique_control_sets_used=2</TD>
<TD>unique_control_sets_util_percentage=0.05</TD>
</TR><TR ALIGN='LEFT'> <TD>using_o5_and_o6_fixed=0.05</TD>
<TD>using_o5_and_o6_used=45</TD>
<TD>using_o5_output_only_fixed=45</TD>
<TD>using_o5_output_only_used=0</TD>
</TR><TR ALIGN='LEFT'> <TD>using_o6_output_only_fixed=0</TD>
<TD>using_o6_output_only_used=123</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bscane2_available=4</TD>
<TD>bscane2_fixed=0</TD>
<TD>bscane2_used=0</TD>
<TD>bscane2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>capturee2_available=1</TD>
<TD>capturee2_fixed=0</TD>
<TD>capturee2_used=0</TD>
<TD>capturee2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>dna_port_available=1</TD>
<TD>dna_port_fixed=0</TD>
<TD>dna_port_used=0</TD>
<TD>dna_port_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>efuse_usr_available=1</TD>
<TD>efuse_usr_fixed=0</TD>
<TD>efuse_usr_used=0</TD>
<TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>frame_ecce2_available=1</TD>
<TD>frame_ecce2_fixed=0</TD>
<TD>frame_ecce2_used=0</TD>
<TD>frame_ecce2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>icape2_available=2</TD>
<TD>icape2_fixed=0</TD>
<TD>icape2_used=0</TD>
<TD>icape2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>startupe2_available=1</TD>
<TD>startupe2_fixed=0</TD>
<TD>startupe2_used=0</TD>
<TD>startupe2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>xadc_available=1</TD>
<TD>xadc_fixed=0</TD>
<TD>xadc_used=0</TD>
<TD>xadc_util_percentage=0.00</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>-assert=default::[not_specified]</TD>
<TD>-bufg=default::12</TD>
<TD>-cascade_dsp=default::auto</TD>
<TD>-constrset=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-control_set_opt_threshold=default::auto</TD>
<TD>-directive=default::default</TD>
<TD>-fanout_limit=default::10000</TD>
<TD>-flatten_hierarchy=default::rebuilt</TD>
</TR><TR ALIGN='LEFT'> <TD>-fsm_extraction=default::auto</TD>
<TD>-gated_clock_conversion=default::off</TD>
<TD>-generic=default::[not_specified]</TD>
<TD>-include_dirs=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-keep_equivalent_registers=default::[not_specified]</TD>
<TD>-max_bram=default::-1</TD>
<TD>-max_bram_cascade_height=default::-1</TD>
<TD>-max_dsp=default::-1</TD>
</TR><TR ALIGN='LEFT'> <TD>-max_uram=default::-1</TD>
<TD>-max_uram_cascade_height=default::-1</TD>
<TD>-mode=default::default</TD>
<TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-no_lc=default::[not_specified]</TD>
<TD>-no_srlextract=default::[not_specified]</TD>
<TD>-no_timing_driven=default::[not_specified]</TD>
<TD>-part=xc7z010clg400-1</TD>
</TR><TR ALIGN='LEFT'> <TD>-resource_sharing=default::auto</TD>
<TD>-retiming=default::[not_specified]</TD>
<TD>-rtl=default::[not_specified]</TD>
<TD>-rtl_skip_constraints=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-rtl_skip_ip=default::[not_specified]</TD>
<TD>-seu_protect=default::none</TD>
<TD>-sfcu=default::[not_specified]</TD>
<TD>-shreg_min_size=default::3</TD>
</TR><TR ALIGN='LEFT'> <TD>-top=VGA_top</TD>
<TD>-verilog_define=default::[not_specified]</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'> <TD>elapsed=00:01:36s</TD>
<TD>hls_ip=0</TD>
<TD>memory_gain=948.426MB</TD>
<TD>memory_peak=1310.512MB</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
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