122 lines
3.3 KiB
VHDL
122 lines
3.3 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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library ourTypes;
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use ourTypes.types.all;
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entity RAMController is
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generic(
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snakeDataSize : integer
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);
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Port ( X : in unsigned(5 downto 0);
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Y : in unsigned(4 downto 0);
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request : in std_logic;
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clk : in std_logic;
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output : out nSnakes;
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listRefs : out addresses;
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dataReady : out std_logic := '0';
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matWE : in std_logic;
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matWAddress : in unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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matWData : in std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
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listWE : in std_logic;
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listWAddress : in unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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listWData : in std_logic_vector(snakeDataSize-1 downto 0)
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);
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end RAMController;
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architecture Behavioral of RAMController is
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component snakeRam
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generic(length : integer;
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addressSize : integer;
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dataSize : integer
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);
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Port ( addresses : in addresses;
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clk1 : in std_logic;
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output : out std_logic_vector_array(0 to 8)(dataSize-1 downto 0);
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address2 : in unsigned(addressSize-1 downto 0);
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data2 : in std_logic_vector(dataSize-1 downto 0);
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writeEnable2 : in STD_LOGIC;
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clk2 : in STD_LOGIC
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);
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end component snakeRam;
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signal RAMClk : std_logic; --Pour l'instant c'est la même que H125MHz mais on pourrait avoir besoin de plus
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signal matAddresses : addresses;
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signal refAddresses : std_logic_vector_array(0 to 8)(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal snakeOut : std_logic_vector_array(0 to 8)(snakeDataSize-1 downto 0);
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begin
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SNAKE_RAM : snakeRAM --La RAM pour le snake
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generic map (
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length => MAX_SNAKE,
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addressSize => SNAKE_ADDRESS_SIZE,
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dataSize => snakeDataSize
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)
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port map (
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addresses => to_addresses(refAddresses),
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output => snakeOut,
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clk1 => RAMClk,
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address2 => listWAddress,
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data2 => listWData,
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writeEnable2 => listWE,
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clk2 => clk
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);
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MAT_RAM : snakeRAM --La RAM pour la matrice de correspondance
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generic map (
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length => MAX_SNAKE,
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addressSize => SNAKE_ADDRESS_SIZE,
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dataSize => SNAKE_ADDRESS_SIZE
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)
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port map (
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addresses => matAddresses,
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output => refAddresses,
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clk1 => RAMClk,
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address2 => matWAddress,
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data2 => matWData,
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writeEnable2 => matWE,
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clk2 => clk
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);
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process(clk)
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variable clkCount : integer := 0;
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variable running : boolean := true;
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begin
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if(clk'event and clk = '1') then
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if(request = '1' and not running) then
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running := true;
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dataReady <= '0';
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end if;
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if(running) then
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clkCount := clkCount + 1;
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end if;
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if(clkCount = 3) then
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running := false;
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clkCount := 0;
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dataReady <= '1';
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end if;
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end if;
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end process;
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RAMClk <= clk;
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output <= to_pos(snakeOut);
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listRefs <= matAddresses;
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GENERATEDX : for dx in -1 to 1 generate
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GENERATEDY : for dy in -1 to 1 generate
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matAddresses((dy+1)*3+dx+1) <= to_unsigned(40 * constrain(to_integer(Y) + dy,0,29) + constrain(to_integer(X) + dx,0,39),SNAKE_ADDRESS_SIZE);
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end generate GENERATEDY;
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end generate GENERATEDX;
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end Behavioral;
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