488 lines
14 KiB
VHDL
488 lines
14 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 19.10.2017 08:01:54
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-- Design Name:
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-- Module Name: VGA_top - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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library ourTypes;
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use ourTypes.types.all;
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entity VGA_top is
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Port ( H125MHz : in STD_LOGIC;
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resetGeneral : in std_logic;
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led : out std_logic_vector (3 downto 0);
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vga_hs : out STD_LOGIC;
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vga_vs : out STD_LOGIC;
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vga_r : out STD_LOGIC_VECTOR (4 downto 0);
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vga_g : out STD_LOGIC_VECTOR (5 downto 0);
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vga_b : out STD_LOGIC_VECTOR (4 downto 0);
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button_up : in STD_LOGIC;
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button_down : in STD_LOGIC;
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button_left : in STD_LOGIC;
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button_right : in STD_LOGIC
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);
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end VGA_top;
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architecture Behavioral of VGA_top is
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component clk_wiz_0
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port
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(-- Clock in ports
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clk_in1 : in std_logic;
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-- Clock out ports
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clk_out1 : out std_logic
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);
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end component;
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ATTRIBUTE SYN_BLACK_BOX : BOOLEAN;
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ATTRIBUTE SYN_BLACK_BOX OF clk_wiz_0 : COMPONENT IS TRUE;
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ATTRIBUTE BLACK_BOX_PAD_PIN : STRING;
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ATTRIBUTE BLACK_BOX_PAD_PIN OF clk_wiz_0 : COMPONENT IS "clk_in1,clk_out1";
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component GeneSync is
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Port ( CLK : in std_logic;
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HSYNC : out std_logic;
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VSYNC : out std_logic;
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IMG : out std_logic;
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X : out std_logic_vector(9 downto 0);
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Y : out std_logic_vector(8 downto 0));
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end component;
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component GeneRGB_V1 is
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Port (
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X : in unsigned(9 downto 0);
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Y : in unsigned(8 downto 0);
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IMG : in std_logic;
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R : out std_logic_vector(4 downto 0);
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G : out std_logic_vector(5 downto 0);
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B : out std_logic_vector(4 downto 0);
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snakeIn : in color;
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pommeIn : in color
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);
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end component;
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component Gene_Snake
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generic ( addressSize : integer:=SNAKE_ADDRESS_SIZE);
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Port ( X : in unsigned (9 downto 0);
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Y : in unsigned (8 downto 0);
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clk: in std_logic;
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reset: in std_logic;
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currentSnakes : in nSnakes;
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listRefs : in addresses;
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updateOrder : in std_logic;
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dataReady : in std_logic;
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tailIndex : in unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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cCaseX : out unsigned(5 downto 0);
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cCaseY : out unsigned(4 downto 0);
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dataRequest : out std_logic := '0';
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colorOut : out color;
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ROMAddress : out unsigned(SPRITES_ADDRESS_SIZE-1 downto 0) := (others => '0');
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ROMData : in std_logic_vector(SPRITES_DATA_SIZE-1 downto 0)
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);
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end component Gene_Snake;
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signal dummyPos : pos; --juste pour avoir la taille du type
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component updateSnake
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generic ( dataSize : integer := to_stdlogicvector(dummyPos)'length);
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Port (
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clk_lente : in std_logic;
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clk_rapide : in std_logic;
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reset : in std_logic;
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address : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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dataIn : in std_logic_vector(dataSize-1 downto 0);
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dataOut : out std_logic_vector(dataSize-1 downto 0);
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writeEnable : out std_logic := '1';
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matAddress : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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matDataIn : inout std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
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matDataOut : out std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
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matWriteEnable : out std_logic := '1';
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button_up : in STD_LOGIC;
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button_down : in STD_LOGIC;
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button_left : in STD_LOGIC;
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button_right : in STD_LOGIC;
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pommeCE : out std_logic;
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pommeX : in unsigned(5 downto 0);
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pommeY : in unsigned(4 downto 0);
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resetPomme : out std_logic;
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tailIndex : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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lost : out std_logic
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);
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end component updateSnake;
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component pomme
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generic ( dataSize : integer := to_stdlogicvector(dummyPos)'length);
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Port (
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clk : in std_logic;
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pxl_clk : in std_logic;
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reset : in std_logic;
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CE : in std_logic;
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X : in unsigned (9 downto 0);
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Y : in unsigned (8 downto 0);
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posX : out unsigned(5 downto 0);
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posY : out unsigned(4 downto 0);
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colorOut : out color;
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address : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
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data : in std_logic_vector(dataSize-1 downto 0);
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matAddress : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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matData : in std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
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ROMAddress : out unsigned(7 downto 0) := (others => '0');
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ROMData : in std_logic_vector(SPRITES_DATA_SIZE-1 downto 0)
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);
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end component pomme;
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component RAMController
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generic( snakeDataSize : integer := to_stdlogicvector(dummyPos)'length);
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Port ( X : in unsigned(5 downto 0);
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Y : in unsigned(4 downto 0);
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request : in std_logic;
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clk : in std_logic;
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output : out nSnakes;
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listRefs : out addresses;
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dataReady : out std_logic;
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matWE : in std_logic;
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matWAddress : in unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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matWData : in std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
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matRData : out std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
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listWE : in std_logic;
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listWAddress : in unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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listWData : in std_logic_vector(snakeDataSize-1 downto 0);
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listRData : out std_logic_vector(snakeDataSize-1 downto 0)
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);
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end component RAMController;
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component spritesRom
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generic( addressSize : integer := SPRITES_ADDRESS_SIZE;
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length : integer := SPRITES_DATA_LENGTH;
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dataSize : integer := SPRITES_DATA_SIZE;
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fileName : string := "../projet-electronique/sprites/sprites.mem" --pour l'implementation
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--fileName : string := "../sprites/sprites.mem" --pour la simulation
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);
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Port ( address : in unsigned (addressSize-1 downto 0);
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data : out STD_LOGIC_VECTOR (dataSize-1 downto 0);
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clk : in STD_LOGIC);
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end component spritesRom;
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component Diviseur
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generic (nbBits : integer:=8);
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Port ( clk_in : in STD_LOGIC;
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reset : in STD_LOGIC;
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max : in unsigned (nbBits-1 downto 0);
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clk_out : out STD_LOGIC);
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end component Diviseur;
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signal Xi : std_logic_vector(9 downto 0);
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signal Yi : std_logic_vector(8 downto 0);
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signal Xpxl : unsigned(9 downto 0);
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signal Ypxl : unsigned(8 downto 0);
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signal IMGi : std_logic;
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signal pxl_clk : std_logic;
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signal clk_lente: std_logic;
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--signal valPosX: unsigned (9 downto 0);
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--signal valPosY: unsigned (8 downto 0);
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signal snakeColor: color;
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signal cCaseX : unsigned(5 downto 0);
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signal cCaseY : unsigned(4 downto 0);
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signal dataReady,dataRequest : std_logic;
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signal currentSnakes : nSnakes;
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signal listRefs : addresses;
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signal updateRAMAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal updateRAMDataIn : std_logic_vector(to_stdlogicvector(dummyPos)'length-1 downto 0);
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signal updateRAMDataOut : std_logic_vector(to_stdlogicvector(dummyPos)'length-1 downto 0);
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signal updateRAMWE : std_logic;
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signal updateRAMRE : std_logic;
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signal matupdRAMAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal matupdRAMDataIn : std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal matupdRAMDataOut : std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal matupdRAMWE : std_logic;
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signal matupdRAMRE : std_logic;
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signal RAMAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal RAMDataIn : std_logic_vector(to_stdlogicvector(dummyPos)'length-1 downto 0);
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signal matRAMAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal matRAMDataIn : std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal spritesROMAddress : unsigned(SPRITES_ADDRESS_SIZE-1 downto 0);
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signal spritesROMData : std_logic_vector(SPRITES_DATA_SIZE-1 downto 0);
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signal pommeROMAddress : unsigned(7 downto 0);
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signal pommeROMData : std_logic_vector(SPRITES_DATA_SIZE-1 downto 0);
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signal pommeCE : std_logic;
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signal pommeX : unsigned(5 downto 0);
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signal pommeY : unsigned(4 downto 0);
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signal pommeColor : color;
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signal pommeReset : std_logic;
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signal pommeAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal pommeData : std_logic_vector(to_stdlogicvector(dummyPos)'length-1 downto 0);
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signal pommeMatAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal pommeMatData : std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal tailIndex : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal lost : std_logic;
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--signal clk_latch : std_logic;
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begin
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Xpxl <= unsigned(Xi);
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Ypxl <= unsigned(Yi);
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U0 : clk_wiz_0
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port map (
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-- Clock in ports
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clk_in1 => H125MHz,
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-- Clock out ports
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clk_out1 => pxl_clk
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);
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--Pour la simulation on evite les IP
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--PXL_CLK_DIV : Diviseur
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-- -- in : 125MHz; out : 25MHz; ratio : 5; nbBits : 3
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-- generic map (nbBits => 3)
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-- port map (
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-- clk_in => H125MHz,
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-- reset => resetGeneral,
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-- max => to_unsigned(6,3),
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-- clk_out => pxl_clk
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-- );
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SYNC : GeneSync
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port map(
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CLK => pxl_clk,
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HSYNC => vga_hs,
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VSYNC => vga_vs,
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IMG => IMGi,
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X => Xi,
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Y => Yi);
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RGB : GeneRGB_V1
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port map(
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X => Xpxl,
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Y => Ypxl,
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IMG => IMGi,
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R => vga_r,
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G => vga_g,
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B => vga_b,
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snakeIn => snakeColor,
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pommeIn => pommeColor
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);
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UPD_CLK_DIV : Diviseur
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-- pxl_clock 25MHz, clk_lente ~60Hz, 1 coup sur clk_lente = 25e6/60 = 4.2e5 coups sur pxl_clk. ln(4.2e5)/ln(2)=18.6, donc on prend 19bits
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generic map (nbBits => 25)
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port map (
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clk_in => pxl_clk,
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reset => resetGeneral,
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max => to_unsigned(420000,25),
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--max => to_unsigned(25000000,25),
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--max => to_unsigned(1000,25),
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--max => (others => '0'),
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clk_out => clk_lente
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);
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SNAKE : Gene_Snake
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port map (
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X => Xpxl,
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Y => Ypxl,
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clk => H125Mhz,
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reset => resetGeneral,
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currentSnakes => currentSnakes,
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listRefs => listRefs,
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updateOrder => pxl_clk,
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dataReady => dataReady,
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tailIndex => tailIndex,
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cCaseX => cCaseX,
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cCaseY => cCaseY,
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dataRequest => dataRequest,
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colorOut => snakeColor,
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ROMAddress => spritesROMAddress,
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ROMData => spritesROMData
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);
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RAMCTRL : RAMController
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port map (
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X => cCaseX,
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Y => cCaseY,
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request => dataRequest,
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clk => H125MHz,
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output => currentSnakes,
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listRefs => listRefs,
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dataReady => dataReady,
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matWE => matupdRAMWE,
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matWaddress => matRAMAddress,
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matWdata => matupdRAMDataOut,
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matRdata => matRAMDataIn,
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listWE => updateRAMWE,
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listWAddress => RAMAddress,
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listWData => updateRAMDataOut,
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listRData => RAMDataIn
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);
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UPD : updateSnake
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port map (
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clk_lente => clk_lente,
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clk_rapide => H125MHz,
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reset => resetGeneral,
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address => updateRAMAddress,
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dataIn => updateRAMDataIn,
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dataOut => updateRAMDataOut,
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writeEnable => updateRAMWE,
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matAddress => matupdRAMAddress,
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matDataIn => matupdRAMDataIn,
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matDataOut => matupdRAMDataOut,
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matWriteEnable => matupdRAMWE,
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button_up => button_up,
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button_down => button_down,
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button_left => button_left,
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button_right => button_right,
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pommeCE => pommeCE,
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pommeX => pommeX,
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pommeY => pommeY,
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resetPomme => pommeReset,
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tailIndex => tailIndex,
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lost => lost
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);
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APPLE : pomme
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port map (
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clk => H125MHz,
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pxl_clk => pxl_clk,
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reset => pommeReset,
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CE => pommeCE,
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X => Xpxl,
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Y => Ypxl,
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posX => pommeX,
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posY => pommeY,
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colorOut => pommeColor,
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address => pommeAddress,
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data => pommeData,
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matAddress => pommeMatAddress,
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matData => pommeMatData,
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ROMAddress => pommeROMAddress,
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ROMData => pommeROMData
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);
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ROM : spritesROM
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generic map(
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addressSize => SPRITES_ADDRESS_SIZE,
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length => SPRITES_DATA_LENGTH,
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dataSize => SPRITES_DATA_SIZE,
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fileName => "../projet-electronique/sprites/sprites.mem" --pour l'implementation
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--fileName => "../sprites/sprites.mem" --pour la simulation
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)
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port map(
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address => spritesROMAddress,
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data => spritesROMData,
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clk => H125MHz
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);
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POMMEROM : spritesROM
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generic map(
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addressSize => 8,
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length => 256,
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dataSize => SPRITES_DATA_SIZE,
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fileName => "../projet-electronique/sprites/pomme.mem" --pour l'implementation
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--fileName => "../sprites/pomme.mem" --pour la simulation
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)
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port map(
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address => pommeROMAddress,
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data => pommeROMData,
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clk => H125MHz
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);
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process(pommeCE,updateRAMAddress,pommeAddress,pommeMatAddress,RAMDataIn,matUpdRAMAddress,matRAMDataIn)
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begin
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if(pommeCE = '0') then
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RAMAddress <= updateRAMAddress;
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updateRAMDataIn <= RAMDataIn;
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matRAMAddress <= matUpdRAMAddress;
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matUpdRAMDataIn <= matRAMDataIn;
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pommeData <= (others => '0');
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pommeMatData <= (others => '0');
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else
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RAMAddress <= pommeAddress;
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pommeData <= RAMDataIn;
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matRAMAddress <= pommeMatAddress;
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pommeMatData <= matRAMDataIn;
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updateRAMDataIn <= (others => '0');
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matUpdRAMDataIn <= (others => '0');
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end if;
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end process;
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led(0) <= resetGeneral;
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led(1) <= updateRAMWE;
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led(2) <= clk_lente;
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led(3) <= lost;
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end Behavioral;
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