88 lines
2.2 KiB
VHDL
88 lines
2.2 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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entity testbench is
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end testbench;
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architecture Behavioral of testbench is
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component VGA_top is
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Port ( H125MHz : in STD_LOGIC;
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resetGeneral : in std_logic;
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led : out std_logic_vector (3 downto 0);
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vga_hs : out STD_LOGIC;
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vga_vs : out STD_LOGIC;
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vga_r : out STD_LOGIC_VECTOR (4 downto 0);
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vga_g : out STD_LOGIC_VECTOR (5 downto 0);
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vga_b : out STD_LOGIC_VECTOR (4 downto 0);
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button_up : in STD_LOGIC;
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button_down : in STD_LOGIC;
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button_left : in STD_LOGIC;
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button_right : in STD_LOGIC
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);
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end component;
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constant clk_period : time := 8 ns;
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signal clk : std_logic := '0';
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signal HS : std_logic;
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signal VS : std_logic;
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signal R : STD_LOGIC_VECTOR (4 downto 0);
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signal G : STD_LOGIC_VECTOR (5 downto 0);
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signal B : STD_LOGIC_VECTOR (4 downto 0);
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signal bl,br,bu,bd : STD_LOGIC := '0';
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begin
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U0 : VGA_top
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port map(H125MHz => clk,
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resetGeneral => '1',
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led => open,
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vga_hs => HS,
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vga_vs => VS,
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vga_r => R,
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vga_g => G,
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vga_b => B,
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button_up => bu,
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button_down => bd,
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button_left => bl,
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button_right => br
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);
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clk <= not clk after clk_period/2;
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process (clk)
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file file_pointer: text open write_mode is "write.txt";
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variable line_el: line;
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begin
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if rising_edge(clk) then
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write(line_el, now); -- write the line.
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write(line_el, string'(":")); -- write the line.
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write(line_el, string'(" "));
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write(line_el, HS); -- write the line.
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write(line_el, string'(" "));
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write(line_el, VS); -- write the line.
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write(line_el, string'(" "));
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write(line_el, R & '0'); -- write the line.
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write(line_el, string'(" "));
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write(line_el, G); -- write the line.
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write(line_el, string'(" "));
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write(line_el, B & '0'); -- write the line.
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writeline(file_pointer, line_el); -- write the contents into the file.
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case << signal .U0.SYNC.frameCount : integer >> is
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when 50 => br <= '1';
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when others => br <= '0';
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end case;
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end if;
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end process;
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end Behavioral;
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