524 lines
28 KiB
Plaintext
524 lines
28 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Tue Nov 30 12:02:04 2021
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# Process ID: 12280
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# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
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# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
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# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
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# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
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#-----------------------------------------------------------
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source VGA_top.tcl -notrace
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Command: link_design -top VGA_top -part xc7z010clg400-1
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Design is defaulting to srcset: sources_1
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Design is defaulting to constrset: constrs_1
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INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
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INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
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INFO: [Project 1-479] Netlist was created with Vivado 2018.3
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INFO: [Device 21-403] Loading part xc7z010clg400-1
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
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Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
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Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
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INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
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INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
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get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1224.238 ; gain = 533.496
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Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
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Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
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Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1224.238 ; gain = 0.000
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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link_design completed successfully
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link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1224.238 ; gain = 861.020
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Command: opt_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
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Running DRC as a precondition to command opt_design
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Starting DRC Task
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Project 1-461] DRC finished with 0 Errors
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INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.499 . Memory (MB): peak = 1224.238 ; gain = 0.000
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Starting Cache Timing Information Task
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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INFO: [Timing 38-2] Deriving generated clocks
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Ending Cache Timing Information Task | Checksum: d1b7283d
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1241.336 ; gain = 17.098
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Starting Logic Optimization Task
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Phase 1 Retarget
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Opt 31-49] Retargeted 0 cell(s).
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Phase 1 Retarget | Checksum: d1b7283d
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1327.883 ; gain = 0.000
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INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
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INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
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Phase 2 Constant propagation
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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Phase 2 Constant propagation | Checksum: d1b7283d
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1327.883 ; gain = 0.000
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INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
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Phase 3 Sweep
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Phase 3 Sweep | Checksum: 4c4916a3
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1327.883 ; gain = 0.000
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INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
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Phase 4 BUFG optimization
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INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
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INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
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Phase 4 BUFG optimization | Checksum: ea635365
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1327.883 ; gain = 0.000
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INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
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Phase 5 Shift Register Optimization
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Phase 5 Shift Register Optimization | Checksum: 189961a21
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1327.883 ; gain = 0.000
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INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
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Phase 6 Post Processing Netlist
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Phase 6 Post Processing Netlist | Checksum: fdaedd04
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1327.883 ; gain = 0.000
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INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
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Opt_design Change Summary
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=========================
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-------------------------------------------------------------------------------------------------------------------------
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| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
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-------------------------------------------------------------------------------------------------------------------------
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| Retarget | 0 | 0 | 1 |
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| Constant propagation | 0 | 0 | 0 |
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| Sweep | 0 | 0 | 0 |
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| BUFG optimization | 0 | 0 | 0 |
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| Shift Register Optimization | 0 | 0 | 0 |
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| Post Processing Netlist | 0 | 0 | 0 |
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-------------------------------------------------------------------------------------------------------------------------
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Starting Connectivity Check Task
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Ending Logic Optimization Task | Checksum: 1a5a98288
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Starting Power Optimization Task
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INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
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Ending Power Optimization Task | Checksum: 1a5a98288
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Starting Final Cleanup Task
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Ending Final Cleanup Task | Checksum: 1a5a98288
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Starting Netlist Obfuscation Task
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Ending Netlist Obfuscation Task | Checksum: 1a5a98288
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
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INFO: [Common 17-83] Releasing license: Implementation
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30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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opt_design completed successfully
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing placer database...
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
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Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
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INFO: [IP_Flow 19-1839] IP Catalog is up to date.
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
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report_drc completed successfully
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Command: place_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Running DRC as a precondition to command place_design
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Placer Task
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INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
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Phase 1 Placer Initialization
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Phase 1.1 Placer Initialization Netlist Sorting
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 1.1 Placer Initialization Netlist Sorting | Checksum: f74f5d31
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: dff97cf7
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.238 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 1.3 Build Placer Netlist Model
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Phase 1.3 Build Placer Netlist Model | Checksum: 1427c2c70
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.291 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 1.4 Constrain Clocks/Macros
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Phase 1.4 Constrain Clocks/Macros | Checksum: 1427c2c70
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.292 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 1 Placer Initialization | Checksum: 1427c2c70
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.293 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 2 Global Placement
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Phase 2.1 Floorplanning
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Phase 2.1 Floorplanning | Checksum: fef86770
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.335 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 2.2 Physical Synthesis In Placer
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INFO: [Physopt 32-65] No nets found for high-fanout optimization.
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INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
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INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
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INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
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INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
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INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
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INFO: [Physopt 32-949] No candidate nets found for HD net replication
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INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Summary of Physical Synthesis Optimizations
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============================================
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----------------------------------------------------------------------------------------------------------------------------------------
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| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
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----------------------------------------------------------------------------------------------------------------------------------------
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| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
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| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
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| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
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| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
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| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
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| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
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----------------------------------------------------------------------------------------------------------------------------------------
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Phase 2.2 Physical Synthesis In Placer | Checksum: 1ace7cfcc
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.633 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 2 Global Placement | Checksum: 141a32296
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.643 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 3 Detail Placement
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Phase 3.1 Commit Multi Column Macros
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Phase 3.1 Commit Multi Column Macros | Checksum: 141a32296
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.644 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 3.2 Commit Most Macros & LUTRAMs
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Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 78fa4a02
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.691 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 3.3 Area Swap Optimization
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Phase 3.3 Area Swap Optimization | Checksum: d7dfc3b7
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.694 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 3.4 Pipeline Register Optimization
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Phase 3.4 Pipeline Register Optimization | Checksum: d7dfc3b7
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.695 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 3.5 Small Shape Detail Placement
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Phase 3.5 Small Shape Detail Placement | Checksum: 12debda8c
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.741 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 3.6 Re-assign LUT pins
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Phase 3.6 Re-assign LUT pins | Checksum: 14ae64a6f
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.744 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 3.7 Pipeline Register Optimization
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Phase 3.7 Pipeline Register Optimization | Checksum: 14ae64a6f
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.744 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 3 Detail Placement | Checksum: 14ae64a6f
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.745 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 4 Post Placement Optimization and Clean-Up
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Phase 4.1 Post Commit Optimization
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Phase 4.1.1 Post Placement Optimization
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Post Placement Optimization Initialization | Checksum: 1cebea503
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Phase 4.1.1.1 BUFG Insertion
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INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
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Phase 4.1.1.1 BUFG Insertion | Checksum: 1cebea503
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.774 . Memory (MB): peak = 1327.883 ; gain = 0.000
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INFO: [Place 30-746] Post Placement Timing Summary WNS=36.129. For the most accurate timing information please run report_timing.
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Phase 4.1.1 Post Placement Optimization | Checksum: 20987d072
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.775 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 4.1 Post Commit Optimization | Checksum: 20987d072
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.775 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 4.2 Post Placement Cleanup
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Phase 4.2 Post Placement Cleanup | Checksum: 20987d072
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.776 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 4.3 Placer Reporting
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Phase 4.3 Placer Reporting | Checksum: 20987d072
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.777 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 4.4 Final Placement Cleanup
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 4.4 Final Placement Cleanup | Checksum: 27c4f344f
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.779 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Phase 4 Post Placement Optimization and Clean-Up | Checksum: 27c4f344f
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.779 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Ending Placer Task | Checksum: 1ab889c44
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.780 . Memory (MB): peak = 1327.883 ; gain = 0.000
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INFO: [Common 17-83] Releasing license: Implementation
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57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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place_design completed successfully
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing placer database...
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
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report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1327.883 ; gain = 0.000
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INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
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INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
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report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1327.883 ; gain = 0.000
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Command: route_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
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Running DRC as a precondition to command route_design
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Routing Task
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INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
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Checksum: PlaceDB: e36d3f86 ConstDB: 0 ShapeSum: c81b5cbe RouteDB: 0
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Phase 1 Build RT Design
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Phase 1 Build RT Design | Checksum: 408a135c
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1399.160 ; gain = 71.277
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Post Restoration Checksum: NetGraph: 2bba0e1e NumContArr: 14d0053e Constraints: 0 Timing: 0
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Phase 2 Router Initialization
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Phase 2.1 Create Timer
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Phase 2.1 Create Timer | Checksum: 408a135c
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1423.402 ; gain = 95.520
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Phase 2.2 Fix Topology Constraints
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Phase 2.2 Fix Topology Constraints | Checksum: 408a135c
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.410 ; gain = 101.527
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Phase 2.3 Pre Route Cleanup
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Phase 2.3 Pre Route Cleanup | Checksum: 408a135c
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.410 ; gain = 101.527
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Number of Nodes with overlaps = 0
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Phase 2.4 Update Timing
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Phase 2.4 Update Timing | Checksum: 193e9052a
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1432.094 ; gain = 104.211
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INFO: [Route 35-416] Intermediate Timing Summary | WNS=36.042 | TNS=0.000 | WHS=-0.250 | THS=-3.548 |
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Phase 2 Router Initialization | Checksum: 196977bdb
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1432.094 ; gain = 104.211
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Phase 3 Initial Routing
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Phase 3 Initial Routing | Checksum: 14455b7e9
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1432.094 ; gain = 104.211
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Phase 4 Rip-up And Reroute
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Phase 4.1 Global Iteration 0
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Number of Nodes with overlaps = 4
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Number of Nodes with overlaps = 0
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INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.940 | TNS=0.000 | WHS=N/A | THS=N/A |
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Phase 4.1 Global Iteration 0 | Checksum: e844e306
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211
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Phase 4 Rip-up And Reroute | Checksum: e844e306
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211
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Phase 5 Delay and Skew Optimization
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Phase 5.1 Delay CleanUp
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Phase 5.1 Delay CleanUp | Checksum: e844e306
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211
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Phase 5.2 Clock Skew Optimization
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Phase 5.2 Clock Skew Optimization | Checksum: e844e306
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211
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Phase 5 Delay and Skew Optimization | Checksum: e844e306
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211
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Phase 6 Post Hold Fix
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Phase 6.1 Hold Fix Iter
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Phase 6.1.1 Update Timing
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Phase 6.1.1 Update Timing | Checksum: 9a801cee
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211
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INFO: [Route 35-416] Intermediate Timing Summary | WNS=36.093 | TNS=0.000 | WHS=0.063 | THS=0.000 |
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Phase 6.1 Hold Fix Iter | Checksum: 9a801cee
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211
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Phase 6 Post Hold Fix | Checksum: 9a801cee
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211
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Phase 7 Route finalize
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Router Utilization Summary
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Global Vertical Routing Utilization = 0.0209741 %
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Global Horizontal Routing Utilization = 0.00827206 %
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Routable Net Status*
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*Does not include unroutable nets such as driverless and loadless.
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Run report_route_status for detailed report.
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Number of Failed Nets = 0
|
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Number of Unrouted Nets = 0
|
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Number of Partially Routed Nets = 0
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Number of Node Overlaps = 0
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Phase 7 Route finalize | Checksum: 12bf57e3c
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211
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Phase 8 Verifying routed nets
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Verification completed successfully
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Phase 8 Verifying routed nets | Checksum: 12bf57e3c
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1433.680 ; gain = 105.797
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Phase 9 Depositing Routes
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Phase 9 Depositing Routes | Checksum: f9632067
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1433.680 ; gain = 105.797
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Phase 10 Post Router Timing
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INFO: [Route 35-57] Estimated Timing Summary | WNS=36.093 | TNS=0.000 | WHS=0.063 | THS=0.000 |
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INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
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Phase 10 Post Router Timing | Checksum: f9632067
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1433.680 ; gain = 105.797
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INFO: [Route 35-16] Router Completed Successfully
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Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1433.680 ; gain = 105.797
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Routing Is Done.
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INFO: [Common 17-83] Releasing license: Implementation
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74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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route_design completed successfully
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route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:23 . Memory (MB): peak = 1433.680 ; gain = 105.797
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1433.680 ; gain = 0.000
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing placer database...
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Writing XDEF routing.
|
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
|
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1433.680 ; gain = 0.000
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1433.793 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
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Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
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INFO: [IP_Flow 19-1839] IP Catalog is up to date.
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
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report_drc completed successfully
|
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INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
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Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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INFO: [DRC 23-133] Running Methodology with 2 threads
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INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
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report_methodology completed successfully
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INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
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Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Running Vector-less Activity Propagation...
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Finished Running Vector-less Activity Propagation
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86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
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report_power completed successfully
|
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INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
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INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
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INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
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INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
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INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
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INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
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INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
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INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
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INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
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INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
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INFO: [Common 17-206] Exiting Vivado at Tue Nov 30 12:02:53 2021...
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