77 lines
1.9 KiB
VHDL
77 lines
1.9 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12/16/2021 09:57:33 PM
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-- Design Name:
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-- Module Name: snakeRam - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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library ourTypes;
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use ourTypes.types.all;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity snakeRam is
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generic (
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length : integer;
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addressSize : integer;
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dataSize : integer
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);
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Port ( addresses : in addresses;
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clk1 : in std_logic;
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output : out std_logic_vector_array(0 to 8)(dataSize-1 downto 0);
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address2 : in unsigned(addressSize-1 downto 0);
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data2 : in std_logic_vector(dataSize-1 downto 0);
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writeEnable2 : in STD_LOGIC;
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clk2 : in STD_LOGIC);
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end snakeRam;
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architecture Behavioral of snakeRam is
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type listData is array(0 to length-1) of std_logic_vector(dataSize-1 downto 0);
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signal mem : listData := (others => (others => '0'));
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begin
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process(clk1)
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begin
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if(clk1'event and clk1 = '1') then
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for i in addresses'LOW to addresses'HIGH loop
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output(i) <= mem(to_integer(addresses(i)));
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end loop;
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end if;
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end process;
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process(clk2)
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begin
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if(clk2'event and clk2 = '1') then
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-- data2 <= mem(to_integer(address2));
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if(writeEnable2 = '1') then
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mem(to_integer(address2)) <= data2;
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end if;
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end if;
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end process;
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end Behavioral;
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