18 lines
582 B
Plaintext
18 lines
582 B
Plaintext
# compile vhdl design source files
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vhdl xil_defaultlib \
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"../../../../../projet_vga_etn_sources/Diviseur.vhd" \
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"../../../../../projet_vga_etn_sources/GeneRGB_V1.vhd" \
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"../../../../../projet_vga_etn_sources/GeneSync.vhd" \
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vhdl ourTypes \
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"../../../../../projet_vga_etn_sources/types.vhd" \
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vhdl xil_defaultlib \
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"../../../../../projet_vga_etn_sources/Gene_Snake.vhd" \
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"../../../../ETN_snake.srcs/sources_1/new/snakeRam.vhd" \
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"../../../../../projet_vga_etn_sources/updateSnake.vhd" \
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"../../../../../projet_vga_etn_sources/VGA_top.vhd" \
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# Do not sort compile order
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nosort
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