57 lines
1.3 KiB
VHDL
57 lines
1.3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 16.11.2021 11:35:27
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-- Design Name:
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-- Module Name: Gene_Balle - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Gene_Balle is
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Port ( X : in unsigned (9 downto 0);
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Y : in unsigned (8 downto 0);
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ballePresente : out std_logic;
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PosX : in unsigned (9 downto 0);
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PosY : in unsigned (8 downto 0));
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end Gene_Balle;
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architecture Behavioral of Gene_Balle is
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begin
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process(X,Y,PosX, PosY)
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begin
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if (PosX - 10 <=X and X<=PosX + 10 and PosY - 10<=Y and Y<=PosY + 10) then
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ballePresente <= '1';
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else
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ballePresente <= '0';
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end if;
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end process;
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end Behavioral;
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