145 lines
3.6 KiB
VHDL
145 lines
3.6 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 16.11.2021 12:02:26
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-- Design Name:
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-- Module Name: Gene_Position - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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-- Ce qui manque certainement:
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-- - le composant clk_wiz0
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-- - le composant Gene_RGB
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-- - des signaux (en particulier X et Y)
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entity VGA_top is
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Port ( button_up : in STD_LOGIC;
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button_down : in STD_LOGIC;
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button_left : in STD_LOGIC;
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button_right : in STD_LOGIC;
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H125Mhz: in STD_LOGIC;
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resetGeneral: in STD_LOGIC;
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);
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end VGA_top;
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architecture Behavioral of VGA_top is
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-- Déclaration des composants
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component Gene_Position
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Port ( up : in STD_LOGIC;
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down : in STD_LOGIC;
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left : in STD_LOGIC;
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right : in STD_LOGIC;
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clk: in STD_LOGIC;
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reset: in STD_LOGIC;
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PosX : out unsigned (9 downto 0);
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PosY : out unsigned (8 downto 0));
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end component Gene_Position;
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component Diviseur
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generic (nbBits : integer:=8);
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Port ( clk_in : in STD_LOGIC;
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reset : in STD_LOGIC;
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max : in unsigned (nbBits-1 downto 0);
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clk_out : out STD_LOGIC);
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end component Diviseur;
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component Gene_Balle
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Port ( X : in unsigned (9 downto 0);
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Y : in unsigned (8 downto 0);
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PosX : in unsigned (9 downto 0);
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PosY : in unsigned (8 downto 0);
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ballePresente : out std_logic);
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end component Gene_Balle;
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component Gene_Snake
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Port ( X : in unsigned (9 downto 0);
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Y : in unsigned (8 downto 0);
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up : in std_logic;
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down : in std_logic;
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left : in std_logic;
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right : in std_logic;
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clk_rapide: in std_logic;
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clk_lente : in std_logic;
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reset: in std_logic;
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snakePresent : out std_logic);
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end component Gene_Snake;
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-- Déclaration des signaux
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signal clk_lente: std_logic;
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signal valPosX: unsigned (9 downto 0);
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signal valPosY: unsigned (8 downto 0);
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signal valBallePresente: std_logic;
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begin
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U1 : Gene_Position
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port map (
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up => button_up,
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down => button_down,
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left => button_left,
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right => button_right,
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clk => clk_lente,
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reset => resetGeneral,
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PosX => valPosX,
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PosY => valPosY
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);
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U2 : Diviseur
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-- je n'ai plus le souvenir du bon nombre de bits ici
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generic map (nbBits => 11)
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port map (
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clk_in => H125Mhz,
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reset => resetGeneral,
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-- ne pense pas que ce soit bon ici
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-- on avait surement branché autre chose à "max"
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max => unsigned (nbBits - 1 downto 0),
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clk_out => clk_lente
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);
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-- U3 : Gene_Balle
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-- port map (
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-- X => ,
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-- Y => ,
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-- PosX => ,
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-- PosY => ,
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-- ballePresente => valBallePresente
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-- );
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U4 : Gene_Snake
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port map (
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X => ,
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Y => ,
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up => button_up,
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down => button_down,
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left => button_left,
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right => button_right,
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clk_lente => clk_lente,
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clk_rapide => H125Mhz,
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reset => resetGeneral,
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snakePresent => valBallePresente
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);
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end Behavioral; |