45 lines
1.8 KiB
VHDL
45 lines
1.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package types is
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constant MAX_SNAKE : integer := 1200;
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constant SNAKE_ADDRESS_SIZE : integer :=11;
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type coord is array(0 to 39, 0 to 29) of unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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type pos is record
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X: unsigned(9 downto 0);
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Y: unsigned(8 downto 0);
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dirX: signed(1 downto 0);
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dirY: signed(1 downto 0);
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isDefined: std_logic;
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end record;
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function to_stdlogicvector(snake : pos) return std_logic_vector;
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function to_pos(input : std_logic_vector) return pos;
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end package;
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package body types is
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function to_stdlogicvector(snake : pos) return std_logic_vector is
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--variable sortie : std_logic_vector(pos.X'length+pos.Y'length+pos.dirX'length+pos.dirY'length downto 0);
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begin
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return std_logic_vector(std_logic_vector(snake.X) & std_logic_vector(snake.Y) & std_logic_vector(snake.dirX) & std_logic_vector(snake.dirY) & snake.isDefined);
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end to_stdlogicvector;
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function to_pos(input : std_logic_vector) return pos is
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variable sortie : pos;
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variable offset : integer;
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begin
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--si on trouve une facon plus simple de deserialiser je suis preneur
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offset := 0;
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sortie.isDefined := input(0);
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offset := offset+1;
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sortie.dirY := signed(input(offset+pos.dirY'length-1 downto offset));
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offset := offset+pos.dirY'length;
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sortie.dirX := signed(input(offset+pos.dirX'length-1 downto offset));
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offset := offset+pos.dirX'length;
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sortie.Y := unsigned(input(offset+pos.Y'length-1 downto offset));
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offset := offset+pos.Y'length;
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sortie.X := unsigned(input(offset+pos.X'length-1 downto offset));
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return sortie;
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end to_pos;
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end package body;
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