128 lines
3.8 KiB
VHDL
128 lines
3.8 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 01/08/2022 10:04:42 PM
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-- Design Name:
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-- Module Name: pomme - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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library ourTypes;
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use ourTypes.types.all;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity pomme is
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generic ( dataSize : integer);
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Port (
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clk : in std_logic;
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pxl_clk : in std_logic;
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reset : in std_logic;
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CE : in std_logic;
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X : in unsigned (9 downto 0);
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Y : in unsigned (8 downto 0);
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posX : out unsigned(5 downto 0);
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posY : out unsigned(4 downto 0);
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colorOut : out color;
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address : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
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data : in std_logic_vector(dataSize-1 downto 0);
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matAddress : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
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matData : in std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
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ROMAddress : out unsigned(7 downto 0) := (others => '0');
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ROMData : in std_logic_vector(SPRITES_DATA_SIZE-1 downto 0)
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);
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end pomme;
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architecture Behavioral of pomme is
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signal Xpos : unsigned(9 downto 0) := (others => '0');
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signal Ypos : unsigned(8 downto 0) := (others => '0');
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constant FINISHED : unsigned(3 downto 0) := to_unsigned(15,4);
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signal state : unsigned(3 downto 0) := (others => '0');
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signal pommeHere : std_logic;
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begin
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process(clk,reset,CE)
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begin
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if(reset = '0') then
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state <= to_unsigned(0,4);
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elsif(CE = '0') then
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if(state /= FINISHED) then
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state <= to_unsigned(0,4);
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else
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state <= FINISHED;
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end if;
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elsif(rising_edge(clk)) then
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if(state /= FINISHED) then
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state <= state + 1;
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else
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state <= FINISHED;
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end if;
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if(state = 0) then
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Xpos <= (((Xpos + 733) rem 640) and "1111110000") or "0000001000";
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Ypos <= (((Ypos + 587) rem 480) and "111110000") or "000001000";
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elsif(state = 1) then
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matAddress <= to_unsigned(to_integer(Ypos(Ypos'HIGH downto 4)) * 40 + to_integer(Xpos(Xpos'HIGH downto 4)),SNAKE_ADDRESS_SIZE);
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elsif(state = 3) then
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address <= unsigned(matData);
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elsif(state = 5) then
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if(to_pos(data).isDefined = '1') then
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state <= to_unsigned(0,4);
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else
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state <= FINISHED;
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end if;
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end if;
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end if;
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end process;
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process(pxl_clk)
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variable sX,sY : integer;
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begin
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if(rising_edge(pxl_clk)) then
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if(pommeHere = '1') then
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colorOut <= to_color(ROMData);
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else
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colorOut <= (others => (others => '0'));
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end if;
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pommeHere <= '0';
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if(to_integer(X)>=TO_INTEGER(Xpos)-8 and to_integer(X)<TO_INTEGER(Xpos)+8 and to_integer(Y)>=TO_INTEGER(Ypos)-8 and to_integer(Y)<TO_INTEGER(Ypos)+8) then
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pommeHere <= '1';
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sX := (to_integer(X) - to_integer(Xpos)) + 8;
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sY := (to_integer(Y) - to_integer(Ypos)) + 8;
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ROMAddress <= to_unsigned(sY*16+sX,8);
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end if;
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end if;
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end process;
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posX <= Xpos(Xpos'HIGH downto 4);
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posY <= Ypos(Ypos'HIGH downto 4);
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end Behavioral;
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