221 lines
9.1 KiB
VHDL
221 lines
9.1 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12/15/2021 02:06:27 PM
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-- Design Name:
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-- Module Name: updateSnake - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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library ourTypes;
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use ourTypes.types.all;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity updateSnake is
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generic ( dataSize : integer);
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Port (
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clk_lente : in std_logic;
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clk_rapide : in std_logic;
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reset : in std_logic;
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address : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
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dataIn : in std_logic_vector(dataSize-1 downto 0);
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dataOut : out std_logic_vector(dataSize-1 downto 0) := (others => '0');
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writeEnable : out std_logic := '1';
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matAddress : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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matDataIn : in std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
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matDataOut : out std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
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matWriteEnable : out std_logic := '1';
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button_up : in STD_LOGIC;
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button_down : in STD_LOGIC;
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button_left : in STD_LOGIC;
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button_right : in STD_LOGIC;
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pommeCE : out std_logic := '0';
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pommeX : unsigned(5 downto 0);
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pommeY : unsigned(4 downto 0)
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);
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end updateSnake;
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architecture Behavioral of updateSnake is
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signal index : unsigned(SNAKE_ADDRESS_SIZE downto 0) := to_unsigned(0,SNAKE_ADDRESS_SIZE+1);
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signal isUpdating: std_logic := '0';
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signal updateIndex : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
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signal state : unsigned(3 downto 0) := (others => '0');
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begin
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process(updateIndex, clk_rapide, clk_lente,reset,index) --process de reset
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variable cSnake : pos; --current snake, celui qu'on met à jour
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variable lSnake : pos; --last snake, sauvegarde de l'état précédent
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variable pSnake : pos; --previous snake, snake precedent dans la chaine
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variable currentSnake : pos;
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variable update : std_logic := '0';
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variable indext : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := to_unsigned(0,SNAKE_ADDRESS_SIZE);
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variable updateIndext : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
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constant PROG_END : unsigned(3 downto 0) := to_unsigned(15,4);
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begin
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if rising_edge(clk_lente) then
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isUpdating <= '1';
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end if;
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if rising_edge(clk_rapide) then
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indext := index(index'HIGH downto 1);
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updateIndext := MAX_SNAKE - 1 - updateIndex;
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if(reset = '0') then --il faut qu'on ai le reset sur la clk car il controle indirectement l'entrée de la RAM
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index <= (others => '0');
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writeEnable <= '1';
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matWriteEnable <= '1';
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update := '0';
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else
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index <= index + 1;
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if(indext = MAX_SNAKE-1) then
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index <= (others => '0');
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writeEnable <= '0';
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matWriteEnable <= '0';
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update := '1';
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end if;
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end if;
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if(update = '1' and isUpdating = '1') then
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state <= state + 1;
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if(state = 0) then --UPDATE
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writeEnable <= '0';
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address <= updateIndext;
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elsif(state = 2) then
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cSnake := to_pos(dataIn);
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lSnake := to_pos(dataIn);
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if(cSnake.isDefined = '1') then
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cSnake.X := to_unsigned(to_integer(cSnake.X) + to_integer(cSnake.dirX),10);
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cSnake.Y := to_unsigned(to_integer(cSnake.Y) + to_integer(cSnake.dirY),9);
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if(cSnake.X(2 downto 0) = 0 and cSnake.X(3) = '1' and cSnake.Y(2 downto 0) = 0 and cSnake.Y(3) = '1') then --si on est au centre d'une case
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if(updateIndext = 0) then
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if(button_up = '1') then
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cSnake.dirY := to_signed(-1,2);
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cSnake.dirX := to_signed(0,2);
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elsif(button_down = '1') then
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cSnake.dirY := to_signed(1,2);
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cSnake.dirX := to_signed(0,2);
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elsif(button_left = '1') then
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cSnake.dirY := to_signed(0,2);
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cSnake.dirX := to_signed(-1,2);
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elsif(button_right = '1') then
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cSnake.dirY := to_signed(0,2);
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cSnake.dirX := to_signed(1,2);
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end if;
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dataOut <= to_stdlogicvector(cSnake);
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writeEnable <= '1';
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else
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address <= updateIndext-1;
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state <= to_unsigned(9,4);
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end if;
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else
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dataOut <= to_stdlogicvector(cSnake);
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writeEnable <= '1';
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end if;
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else
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state <= PROG_END; --jump end
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end if;
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elsif(state = 4) then -- MAJ MATRICE
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writeEnable <= '0';
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if(cSnake.X(cSnake.X'high downto 4) /= lSnake.X(lSnake.X'high downto 4) or cSnake.Y(cSnake.Y'high downto 4) /= lSnake.Y(lSnake.Y'high downto 4)) then --si on as changé de case
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matWriteEnable <= '1';
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matAddress <= to_unsigned(to_integer(cSnake.Y(cSnake.Y'high downto 4)) * 40 + to_integer(cSnake.X(cSnake.X'high downto 4)),SNAKE_ADDRESS_SIZE);
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matDataOut <= std_logic_vector(updateIndext);
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else
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state <= PROG_END; --jump end
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end if;
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elsif(state = 6) then
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matWriteEnable <= '0';
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matAddress <= to_unsigned(to_integer(lSnake.Y(lSnake.Y'high downto 4)) * 40 + to_integer(lSnake.X(lSnake.X'high downto 4)),SNAKE_ADDRESS_SIZE);
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--matDataOut <= std_logic_vector(updateIndex);
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elsif(state = 8) then
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if(matDataIn = std_logic_vector(to_unsigned(to_integer(lSnake.Y(lSnake.Y'high downto 4)) * 40 + to_integer(lSnake.X(lSnake.X'high downto 4)),SNAKE_ADDRESS_SIZE))) then
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matWriteEnable <= '1';
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matDataOut <= std_logic_vector(to_unsigned(MAX_SNAKE-1,SNAKE_ADDRESS_SIZE));
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end if;
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state <= PROG_END; --jump end
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elsif(state = 10) then -- PROPAGATION DE LA DIRECTION
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pSnake := to_pos(dataIn);
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cSnake.dirX := pSnake.dirX;
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cSnake.dirY := pSnake.dirY;
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dataOut <= to_stdlogicvector(cSnake);
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writeEnable <= '1';
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address <= updateIndext;
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state <= to_unsigned(3,4); --on peut ptet directement jump à la fin?
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elsif(state = PROG_END) then --END
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matWriteEnable <= '0';
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writeEnable <= '0';
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updateIndex <= updateIndex + 1;
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state <= to_unsigned(0,4);
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end if;
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end if;
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if update = '0' then
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if(indext = 0) then
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currentSnake.X := to_unsigned(8+to_integer(indext)*16,10);
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currentSnake.Y := to_unsigned(8,9);
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currentSnake.dirX := to_signed(0,2);
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currentSnake.dirY := to_signed(1,2);
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currentSnake.isDefined := '1';
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elsif(indext < 13) then
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currentSnake.X := to_unsigned(8+to_integer(indext)*16,10);
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currentSnake.Y := to_unsigned(8,9);
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currentSnake.dirX := to_signed(-1,2);
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currentSnake.dirY := to_signed(0,2);
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currentSnake.isDefined := '1';
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else
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currentSnake.X := to_unsigned(8,10);
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currentSnake.Y := to_unsigned(8,9);
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currentSnake.dirX := to_signed(0,2);
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currentSnake.dirY := to_signed(1,2);
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currentSnake.isDefined := '0';
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end if;
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dataOut <= to_stdlogicvector(currentSnake);
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matAddress <= to_unsigned(to_integer(indext),SNAKE_ADDRESS_SIZE);
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matDataOut <= std_logic_vector(to_unsigned(to_integer(indext),SNAKE_ADDRESS_SIZE));
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address <= indext;
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end if;
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if(update = '1' and isUpdating = '0') then
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pommeCE <= '1';
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else
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pommeCE <= '0';
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end if;
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end if;
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if(updateIndex = MAX_SNAKE) then
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isUpdating <= '0';
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updateIndex <= to_unsigned(0,SNAKE_ADDRESS_SIZE);
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state <= to_unsigned(0,4);
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end if;
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end process;
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end Behavioral;
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