68 lines
2.9 KiB
Plaintext
68 lines
2.9 KiB
Plaintext
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
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| Date : Tue Dec 7 12:43:23 2021
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| Host : irb121-02-w running 64-bit major release (build 9200)
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| Command : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
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| Design : VGA_top
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| Device : xc7z010
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Control Set Information
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Table of Contents
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-----------------
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1. Summary
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2. Histogram
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3. Flip-Flop Distribution
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4. Detailed Control Set Information
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1. Summary
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----------
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+----------------------------------------------------------+-------+
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| Status | Count |
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+----------------------------------------------------------+-------+
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| Number of unique control sets | 2 |
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| Unused register locations in slices containing registers | 11 |
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+----------------------------------------------------------+-------+
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2. Histogram
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------------
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+--------+--------------+
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| Fanout | Control Sets |
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+--------+--------------+
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| 10 | 1 |
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| 11 | 1 |
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+--------+--------------+
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3. Flip-Flop Distribution
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-------------------------
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+--------------+-----------------------+------------------------+-----------------+--------------+
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| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
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+--------------+-----------------------+------------------------+-----------------+--------------+
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| No | No | No | 0 | 0 |
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| No | No | Yes | 0 | 0 |
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| No | Yes | No | 11 | 4 |
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| Yes | No | No | 0 | 0 |
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| Yes | No | Yes | 0 | 0 |
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| Yes | Yes | No | 10 | 5 |
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+--------------+-----------------------+------------------------+-----------------+--------------+
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4. Detailed Control Set Information
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-----------------------------------
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+-------------------+---------------+------------------+------------------+----------------+
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| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
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+-------------------+---------------+------------------+------------------+----------------+
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| U0/inst/clk_out1 | U1/eqOp | U1/comptY | 5 | 10 |
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| U0/inst/clk_out1 | | U1/clear | 4 | 11 |
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+-------------------+---------------+------------------+------------------+----------------+
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