5527 lines
411 KiB
Plaintext
5527 lines
411 KiB
Plaintext
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
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| Date : Tue Dec 7 12:43:48 2021
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| Host : irb121-02-w running 64-bit major release (build 9200)
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| Command : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
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| Design : VGA_top
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| Device : 7z010-clg400
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| Speed File : -1 PRODUCTION 1.11 2014-09-11
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--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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Timing Summary Report
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------------------------------------------------------------------------------------------------
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| Timer Settings
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| --------------
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------------------------------------------------------------------------------------------------
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Enable Multi Corner Analysis : Yes
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Enable Pessimism Removal : Yes
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Pessimism Removal Resolution : Nearest Common Node
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Enable Input Delay Default Clock : No
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Enable Preset / Clear Arcs : No
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Disable Flight Delays : No
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Ignore I/O Paths : No
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Timing Early Launch at Borrowing Latches : false
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Corner Analyze Analyze
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Name Max Paths Min Paths
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------ --------- ---------
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Slow Yes Yes
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Fast Yes Yes
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check_timing report
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Table of Contents
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-----------------
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1. checking no_clock
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2. checking constant_clock
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3. checking pulse_width_clock
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4. checking unconstrained_internal_endpoints
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5. checking no_input_delay
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6. checking no_output_delay
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7. checking multiple_clock
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8. checking generated_clocks
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9. checking loops
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10. checking partial_input_delay
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11. checking partial_output_delay
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12. checking latch_loops
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1. checking no_clock
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--------------------
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There are 0 register/latch pins with no clock.
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2. checking constant_clock
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--------------------------
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There are 0 register/latch pins with constant_clock.
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3. checking pulse_width_clock
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-----------------------------
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There are 0 register/latch pins which need pulse_width check
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4. checking unconstrained_internal_endpoints
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--------------------------------------------
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There are 0 pins that are not constrained for maximum delay.
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There are 0 pins that are not constrained for maximum delay due to constant clock.
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5. checking no_input_delay
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--------------------------
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There are 0 input ports with no input delay specified.
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There are 0 input ports with no input delay but user has a false path constraint.
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6. checking no_output_delay
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---------------------------
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There are 18 ports with no output delay specified. (HIGH)
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There are 0 ports with no output delay but user has a false path constraint
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There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
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7. checking multiple_clock
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--------------------------
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There are 21 register/latch pins with multiple clocks. (HIGH)
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8. checking generated_clocks
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----------------------------
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There are 0 generated clocks that are not connected to a clock source.
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9. checking loops
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-----------------
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There are 0 combinational loops in the design.
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10. checking partial_input_delay
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--------------------------------
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There are 0 input ports with partial input delay specified.
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11. checking partial_output_delay
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---------------------------------
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There are 0 ports with partial output delay specified.
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12. checking latch_loops
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------------------------
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There are 0 combinational latch loops in the design through latch input
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------------------------------------------------------------------------------------------------
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| Design Timing Summary
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| ---------------------
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------------------------------------------------------------------------------------------------
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WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
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------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
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33.269 0.000 0 52 0.101 0.000 0 52 2.000 0.000 0 27
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All user specified timing constraints are met.
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------------------------------------------------------------------------------------------------
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| Clock Summary
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| -------------
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------------------------------------------------------------------------------------------------
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Clock Waveform(ns) Period(ns) Frequency(MHz)
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----- ------------ ---------- --------------
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H125MHz {0.000 4.000} 8.000 125.000
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clk_out1_clk_wiz_1 {0.000 20.000} 40.000 25.000
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clkfbout_clk_wiz_1 {0.000 20.000} 40.000 25.000
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sys_clk_pin {0.000 4.000} 8.000 125.000
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clk_out1_clk_wiz_1_1 {0.000 20.000} 40.000 25.000
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clkfbout_clk_wiz_1_1 {0.000 20.000} 40.000 25.000
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------------------------------------------------------------------------------------------------
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| Intra Clock Table
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| -----------------
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------------------------------------------------------------------------------------------------
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Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
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----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
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H125MHz 2.000 0.000 0 1
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clk_out1_clk_wiz_1 33.269 0.000 0 52 0.261 0.000 0 52 19.500 0.000 0 23
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clkfbout_clk_wiz_1 37.845 0.000 0 3
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sys_clk_pin 2.000 0.000 0 1
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clk_out1_clk_wiz_1_1 33.281 0.000 0 52 0.261 0.000 0 52 19.500 0.000 0 23
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clkfbout_clk_wiz_1_1 37.845 0.000 0 3
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------------------------------------------------------------------------------------------------
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| Inter Clock Table
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| -----------------
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------------------------------------------------------------------------------------------------
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From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
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---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
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clk_out1_clk_wiz_1_1 clk_out1_clk_wiz_1 33.269 0.000 0 52 0.101 0.000 0 52
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clk_out1_clk_wiz_1 clk_out1_clk_wiz_1_1 33.269 0.000 0 52 0.101 0.000 0 52
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------------------------------------------------------------------------------------------------
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| Other Path Groups Table
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| -----------------------
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------------------------------------------------------------------------------------------------
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Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
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---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
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------------------------------------------------------------------------------------------------
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| Timing Details
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------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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From Clock: H125MHz
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To Clock: H125MHz
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Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
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Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
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PW : 0 Failing Endpoints, Worst Slack 2.000ns, Total Violation 0.000ns
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---------------------------------------------------------------------------------------------------
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Pulse Width Checks
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--------------------------------------------------------------------------------------
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Clock Name: H125MHz
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Waveform(ns): { 0.000 4.000 }
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Period(ns): 8.000
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Sources: { H125MHz }
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Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
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Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 8.000 6.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1
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Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 8.000 92.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1
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Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1
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Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1
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High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1
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High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1
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---------------------------------------------------------------------------------------------------
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From Clock: clk_out1_clk_wiz_1
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To Clock: clk_out1_clk_wiz_1
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Setup : 0 Failing Endpoints, Worst Slack 33.269ns, Total Violation 0.000ns
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Hold : 0 Failing Endpoints, Worst Slack 0.261ns, Total Violation 0.000ns
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PW : 0 Failing Endpoints, Worst Slack 19.500ns, Total Violation 0.000ns
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---------------------------------------------------------------------------------------------------
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Max Delay Paths
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--------------------------------------------------------------------------------------
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Slack (MET) : 33.269ns (required time - arrival time)
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Source: U1/comptY_reg[5]/C
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(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
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Destination: U1/comptY_reg[3]/R
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(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
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Path Group: clk_out1_clk_wiz_1
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
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Data Path Delay: 6.142ns (logic 0.828ns (13.480%) route 5.314ns (86.520%))
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Logic Levels: 3 (LUT4=1 LUT6=2)
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Clock Path Skew: 0.000ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -1.252ns = ( 38.748 - 40.000 )
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Source Clock Delay (SCD): -0.601ns
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Clock Pessimism Removal (CPR): 0.651ns
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Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.313ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock clk_out1_clk_wiz_1 rise edge)
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0.000 0.000 r
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L16 0.000 0.000 r H125MHz (IN)
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net (fo=0) 0.000 0.000 U0/inst/clk_in1
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L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
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net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
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MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
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-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
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net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
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BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
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net (fo=21, routed) 1.758 -0.601 U1/CLK
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SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
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------------------------------------------------------------------- -------------------
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SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
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net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
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SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
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net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
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SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
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net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
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SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
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net (fo=10, routed) 1.866 5.542 U1/comptY
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SLICE_X40Y49 FDRE r U1/comptY_reg[3]/R
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------------------------------------------------------------------- -------------------
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(clock clk_out1_clk_wiz_1 rise edge)
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40.000 40.000 r
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L16 0.000 40.000 r H125MHz (IN)
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net (fo=0) 0.000 40.000 U0/inst/clk_in1
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L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
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net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
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MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
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-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
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net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
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BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
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net (fo=21, routed) 1.580 38.748 U1/CLK
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SLICE_X40Y49 FDRE r U1/comptY_reg[3]/C
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clock pessimism 0.651 39.399
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clock uncertainty -0.160 39.239
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SLICE_X40Y49 FDRE (Setup_fdre_C_R) -0.429 38.810 U1/comptY_reg[3]
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-------------------------------------------------------------------
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required time 38.810
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arrival time -5.542
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-------------------------------------------------------------------
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slack 33.269
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Slack (MET) : 33.269ns (required time - arrival time)
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Source: U1/comptY_reg[5]/C
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(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
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Destination: U1/comptY_reg[5]/R
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(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
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Path Group: clk_out1_clk_wiz_1
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
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Data Path Delay: 6.142ns (logic 0.828ns (13.480%) route 5.314ns (86.520%))
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Logic Levels: 3 (LUT4=1 LUT6=2)
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Clock Path Skew: 0.000ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -1.252ns = ( 38.748 - 40.000 )
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Source Clock Delay (SCD): -0.601ns
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Clock Pessimism Removal (CPR): 0.651ns
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Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.313ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock clk_out1_clk_wiz_1 rise edge)
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0.000 0.000 r
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L16 0.000 0.000 r H125MHz (IN)
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net (fo=0) 0.000 0.000 U0/inst/clk_in1
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L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
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net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
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MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
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-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
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net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
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BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
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net (fo=21, routed) 1.758 -0.601 U1/CLK
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SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
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------------------------------------------------------------------- -------------------
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SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
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net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
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SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
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net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
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SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
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net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
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SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
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net (fo=10, routed) 1.866 5.542 U1/comptY
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SLICE_X40Y49 FDRE r U1/comptY_reg[5]/R
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------------------------------------------------------------------- -------------------
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(clock clk_out1_clk_wiz_1 rise edge)
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40.000 40.000 r
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L16 0.000 40.000 r H125MHz (IN)
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net (fo=0) 0.000 40.000 U0/inst/clk_in1
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L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
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net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
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MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
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-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
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net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
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BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
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net (fo=21, routed) 1.580 38.748 U1/CLK
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SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
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clock pessimism 0.651 39.399
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clock uncertainty -0.160 39.239
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SLICE_X40Y49 FDRE (Setup_fdre_C_R) -0.429 38.810 U1/comptY_reg[5]
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-------------------------------------------------------------------
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required time 38.810
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arrival time -5.542
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-------------------------------------------------------------------
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slack 33.269
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Slack (MET) : 33.414ns (required time - arrival time)
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Source: U1/comptY_reg[5]/C
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(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
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Destination: U1/comptY_reg[4]/R
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(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
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Path Group: clk_out1_clk_wiz_1
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
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Data Path Delay: 5.838ns (logic 0.828ns (14.184%) route 5.010ns (85.816%))
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Logic Levels: 3 (LUT4=1 LUT6=2)
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Clock Path Skew: -0.064ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -1.253ns = ( 38.747 - 40.000 )
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Source Clock Delay (SCD): -0.601ns
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Clock Pessimism Removal (CPR): 0.588ns
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Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.313ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock clk_out1_clk_wiz_1 rise edge)
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0.000 0.000 r
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L16 0.000 0.000 r H125MHz (IN)
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net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.561 5.237 U1/comptY
|
|
SLICE_X38Y49 FDRE r U1/comptY_reg[4]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.579 38.747 U1/CLK
|
|
SLICE_X38Y49 FDRE r U1/comptY_reg[4]/C
|
|
clock pessimism 0.588 39.335
|
|
clock uncertainty -0.160 39.175
|
|
SLICE_X38Y49 FDRE (Setup_fdre_C_R) -0.524 38.651 U1/comptY_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 38.651
|
|
arrival time -5.237
|
|
-------------------------------------------------------------------
|
|
slack 33.414
|
|
|
|
Slack (MET) : 33.600ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[1]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 38.615
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.600
|
|
|
|
Slack (MET) : 33.600ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[2]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[2]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[2]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 38.615
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.600
|
|
|
|
Slack (MET) : 33.600ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[7]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[7]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[7]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 38.615
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.600
|
|
|
|
Slack (MET) : 33.600ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[8]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[8]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[8]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 38.615
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.600
|
|
|
|
Slack (MET) : 33.600ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[9]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[9]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[9]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 38.615
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.600
|
|
|
|
Slack (MET) : 33.744ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[6]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 5.472ns (logic 0.828ns (15.132%) route 4.644ns (84.868%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.196 4.871 U1/comptY
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X36Y50 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 38.615
|
|
arrival time -4.871
|
|
-------------------------------------------------------------------
|
|
slack 33.744
|
|
|
|
Slack (MET) : 33.981ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[0]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 5.139ns (logic 0.828ns (16.112%) route 4.311ns (83.888%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 0.863 4.538 U1/comptY
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X38Y51 FDRE (Setup_fdre_C_R) -0.524 38.520 U1/comptY_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 38.520
|
|
arrival time -4.538
|
|
-------------------------------------------------------------------
|
|
slack 33.981
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.261ns (arrival time - required time)
|
|
Source: U1/comptY_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.368ns (logic 0.183ns (49.756%) route 0.185ns (50.244%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[1]/Q
|
|
net (fo=29, routed) 0.185 -0.148 U1/comptY_reg__0[1]
|
|
SLICE_X36Y51 LUT3 (Prop_lut3_I0_O) 0.042 -0.106 r U1/comptY[2]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.106 U1/comptY[2]_i_1_n_0
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[2]/C
|
|
clock pessimism 0.232 -0.474
|
|
SLICE_X36Y51 FDRE (Hold_fdre_C_D) 0.107 -0.367 U1/comptY_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.367
|
|
arrival time -0.106
|
|
-------------------------------------------------------------------
|
|
slack 0.261
|
|
|
|
Slack (MET) : 0.261ns (arrival time - required time)
|
|
Source: U1/comptX_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[5]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.353ns (logic 0.186ns (52.682%) route 0.167ns (47.318%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.705ns
|
|
Source Clock Delay (SCD): -0.473ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.588 -0.473 U1/CLK
|
|
SLICE_X43Y54 FDRE r U1/comptX_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X43Y54 FDRE (Prop_fdre_C_Q) 0.141 -0.332 r U1/comptX_reg[5]/Q
|
|
net (fo=25, routed) 0.167 -0.165 U1/comptX_reg__0[5]
|
|
SLICE_X43Y54 LUT6 (Prop_lut6_I5_O) 0.045 -0.120 r U1/comptX[5]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.120 U1/plusOp[5]
|
|
SLICE_X43Y54 FDRE r U1/comptX_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.858 -0.705 U1/CLK
|
|
SLICE_X43Y54 FDRE r U1/comptX_reg[5]/C
|
|
clock pessimism 0.232 -0.473
|
|
SLICE_X43Y54 FDRE (Hold_fdre_C_D) 0.092 -0.381 U1/comptX_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 0.381
|
|
arrival time -0.120
|
|
-------------------------------------------------------------------
|
|
slack 0.261
|
|
|
|
Slack (MET) : 0.280ns (arrival time - required time)
|
|
Source: U1/comptX_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[8]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.387ns (logic 0.183ns (47.319%) route 0.204ns (52.681%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q
|
|
net (fo=20, routed) 0.204 -0.129 U1/comptX_reg__0[7]
|
|
SLICE_X41Y57 LUT5 (Prop_lut5_I0_O) 0.042 -0.087 r U1/comptX[8]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.087 U1/plusOp[8]
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[8]/C
|
|
clock pessimism 0.232 -0.474
|
|
SLICE_X41Y57 FDRE (Hold_fdre_C_D) 0.107 -0.367 U1/comptX_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.367
|
|
arrival time -0.087
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (arrival time - required time)
|
|
Source: U1/comptY_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.371ns (logic 0.186ns (50.162%) route 0.185ns (49.838%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[1]/Q
|
|
net (fo=29, routed) 0.185 -0.148 U1/comptY_reg__0[1]
|
|
SLICE_X36Y51 LUT2 (Prop_lut2_I1_O) 0.045 -0.103 r U1/comptY[1]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.103 U1/comptY[1]_i_1_n_0
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C
|
|
clock pessimism 0.232 -0.474
|
|
SLICE_X36Y51 FDRE (Hold_fdre_C_D) 0.091 -0.383 U1/comptY_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.383
|
|
arrival time -0.103
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.288ns (arrival time - required time)
|
|
Source: U1/comptX_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.419ns (logic 0.207ns (49.431%) route 0.212ns (50.569%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.705ns
|
|
Source Clock Delay (SCD): -0.473ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.588 -0.473 U1/CLK
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X42Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.309 r U1/comptX_reg[0]/Q
|
|
net (fo=25, routed) 0.212 -0.097 U1/comptX_reg__0[0]
|
|
SLICE_X42Y55 LUT2 (Prop_lut2_I0_O) 0.043 -0.054 r U1/comptX[1]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.054 U1/plusOp[1]
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.858 -0.705 U1/CLK
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[1]/C
|
|
clock pessimism 0.232 -0.473
|
|
SLICE_X42Y55 FDRE (Hold_fdre_C_D) 0.131 -0.342 U1/comptX_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.342
|
|
arrival time -0.054
|
|
-------------------------------------------------------------------
|
|
slack 0.288
|
|
|
|
Slack (MET) : 0.289ns (arrival time - required time)
|
|
Source: U1/comptX_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[9]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.398ns (logic 0.186ns (46.766%) route 0.212ns (53.234%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.705ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.248ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q
|
|
net (fo=20, routed) 0.212 -0.121 U1/comptX_reg__0[7]
|
|
SLICE_X41Y56 LUT6 (Prop_lut6_I3_O) 0.045 -0.076 r U1/comptX[9]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.076 U1/plusOp[9]
|
|
SLICE_X41Y56 FDRE r U1/comptX_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.858 -0.705 U1/CLK
|
|
SLICE_X41Y56 FDRE r U1/comptX_reg[9]/C
|
|
clock pessimism 0.248 -0.457
|
|
SLICE_X41Y56 FDRE (Hold_fdre_C_D) 0.092 -0.365 U1/comptX_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 0.365
|
|
arrival time -0.076
|
|
-------------------------------------------------------------------
|
|
slack 0.289
|
|
|
|
Slack (MET) : 0.297ns (arrival time - required time)
|
|
Source: U1/comptY_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.402ns (logic 0.183ns (45.514%) route 0.219ns (54.486%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q
|
|
net (fo=21, routed) 0.219 -0.114 U1/comptY_reg__0[6]
|
|
SLICE_X36Y50 LUT3 (Prop_lut3_I2_O) 0.042 -0.072 r U1/comptY[6]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.072 U1/plusOp__0[6]
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C
|
|
clock pessimism 0.232 -0.474
|
|
SLICE_X36Y50 FDRE (Hold_fdre_C_D) 0.105 -0.369 U1/comptY_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 0.369
|
|
arrival time -0.072
|
|
-------------------------------------------------------------------
|
|
slack 0.297
|
|
|
|
Slack (MET) : 0.299ns (arrival time - required time)
|
|
Source: U1/comptX_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.390ns (logic 0.186ns (47.724%) route 0.204ns (52.276%))
|
|
Logic Levels: 1 (LUT4=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q
|
|
net (fo=20, routed) 0.204 -0.129 U1/comptX_reg__0[7]
|
|
SLICE_X41Y57 LUT4 (Prop_lut4_I3_O) 0.045 -0.084 r U1/comptX[7]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.084 U1/plusOp[7]
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C
|
|
clock pessimism 0.232 -0.474
|
|
SLICE_X41Y57 FDRE (Hold_fdre_C_D) 0.091 -0.383 U1/comptX_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 0.383
|
|
arrival time -0.084
|
|
-------------------------------------------------------------------
|
|
slack 0.299
|
|
|
|
Slack (MET) : 0.301ns (arrival time - required time)
|
|
Source: U1/comptY_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[0]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.421ns (logic 0.209ns (49.671%) route 0.212ns (50.329%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X38Y51 FDRE (Prop_fdre_C_Q) 0.164 -0.310 f U1/comptY_reg[0]/Q
|
|
net (fo=29, routed) 0.212 -0.098 U1/comptY_reg__0[0]
|
|
SLICE_X38Y51 LUT1 (Prop_lut1_I0_O) 0.045 -0.053 r U1/comptY[0]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.053 U1/comptY[0]_i_1_n_0
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C
|
|
clock pessimism 0.232 -0.474
|
|
SLICE_X38Y51 FDRE (Hold_fdre_C_D) 0.120 -0.354 U1/comptY_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.354
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.301
|
|
|
|
Slack (MET) : 0.301ns (arrival time - required time)
|
|
Source: U1/comptX_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[0]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.421ns (logic 0.209ns (49.671%) route 0.212ns (50.329%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.705ns
|
|
Source Clock Delay (SCD): -0.473ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.588 -0.473 U1/CLK
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X42Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.309 f U1/comptX_reg[0]/Q
|
|
net (fo=25, routed) 0.212 -0.097 U1/comptX_reg__0[0]
|
|
SLICE_X42Y55 LUT1 (Prop_lut1_I0_O) 0.045 -0.052 r U1/comptX[0]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.052 U1/plusOp[0]
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.858 -0.705 U1/CLK
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C
|
|
clock pessimism 0.232 -0.473
|
|
SLICE_X42Y55 FDRE (Hold_fdre_C_D) 0.120 -0.353 U1/comptX_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.353
|
|
arrival time -0.052
|
|
-------------------------------------------------------------------
|
|
slack 0.301
|
|
|
|
|
|
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: clk_out1_clk_wiz_1
|
|
Waveform(ns): { 0.000 20.000 }
|
|
Period(ns): 40.000
|
|
Sources: { U0/inst/mmcm_adv_inst/CLKOUT0 }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y16 U0/inst/clkout1_buf/I
|
|
Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKOUT0
|
|
Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X42Y55 U1/comptX_reg[0]/C
|
|
Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X41Y56 U1/comptX_reg[10]/C
|
|
Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X42Y55 U1/comptX_reg[1]/C
|
|
Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X43Y54 U1/comptX_reg[2]/C
|
|
Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X43Y54 U1/comptX_reg[3]/C
|
|
Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X41Y56 U1/comptX_reg[4]/C
|
|
Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X38Y51 U1/comptY_reg[0]/C
|
|
Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X36Y51 U1/comptY_reg[1]/C
|
|
Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKOUT0
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X42Y55 U1/comptX_reg[0]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X41Y56 U1/comptX_reg[10]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X42Y55 U1/comptX_reg[1]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X43Y54 U1/comptX_reg[2]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X43Y54 U1/comptX_reg[3]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X41Y56 U1/comptX_reg[4]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X38Y51 U1/comptY_reg[0]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X38Y51 U1/comptY_reg[0]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X36Y51 U1/comptY_reg[1]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X36Y51 U1/comptY_reg[1]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X42Y55 U1/comptX_reg[0]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X41Y56 U1/comptX_reg[10]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X42Y55 U1/comptX_reg[1]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X43Y54 U1/comptX_reg[2]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X43Y54 U1/comptX_reg[3]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X41Y56 U1/comptX_reg[4]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X38Y51 U1/comptY_reg[0]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X36Y51 U1/comptY_reg[1]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X36Y51 U1/comptY_reg[2]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X40Y49 U1/comptY_reg[3]/C
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: clkfbout_clk_wiz_1
|
|
To Clock: clkfbout_clk_wiz_1
|
|
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
PW : 0 Failing Endpoints, Worst Slack 37.845ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: clkfbout_clk_wiz_1
|
|
Waveform(ns): { 0.000 20.000 }
|
|
Period(ns): 40.000
|
|
Sources: { U0/inst/mmcm_adv_inst/CLKFBOUT }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y17 U0/inst/clkf_buf/I
|
|
Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBOUT
|
|
Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBIN
|
|
Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 40.000 60.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBIN
|
|
Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBOUT
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: sys_clk_pin
|
|
To Clock: sys_clk_pin
|
|
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
PW : 0 Failing Endpoints, Worst Slack 2.000ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: sys_clk_pin
|
|
Waveform(ns): { 0.000 4.000 }
|
|
Period(ns): 8.000
|
|
Sources: { H125MHz }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 8.000 6.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1
|
|
Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 8.000 92.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1
|
|
Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1
|
|
Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1
|
|
High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1
|
|
High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: clk_out1_clk_wiz_1_1
|
|
To Clock: clk_out1_clk_wiz_1_1
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 33.281ns, Total Violation 0.000ns
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.261ns, Total Violation 0.000ns
|
|
PW : 0 Failing Endpoints, Worst Slack 19.500ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 33.281ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[3]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 6.142ns (logic 0.828ns (13.480%) route 5.314ns (86.520%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: 0.000ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.252ns = ( 38.748 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.651ns
|
|
Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.286ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.866 5.542 U1/comptY
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[3]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.580 38.748 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[3]/C
|
|
clock pessimism 0.651 39.399
|
|
clock uncertainty -0.147 39.252
|
|
SLICE_X40Y49 FDRE (Setup_fdre_C_R) -0.429 38.823 U1/comptY_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 38.823
|
|
arrival time -5.542
|
|
-------------------------------------------------------------------
|
|
slack 33.281
|
|
|
|
Slack (MET) : 33.281ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[5]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 6.142ns (logic 0.828ns (13.480%) route 5.314ns (86.520%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: 0.000ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.252ns = ( 38.748 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.651ns
|
|
Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.286ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.866 5.542 U1/comptY
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.580 38.748 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
clock pessimism 0.651 39.399
|
|
clock uncertainty -0.147 39.252
|
|
SLICE_X40Y49 FDRE (Setup_fdre_C_R) -0.429 38.823 U1/comptY_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 38.823
|
|
arrival time -5.542
|
|
-------------------------------------------------------------------
|
|
slack 33.281
|
|
|
|
Slack (MET) : 33.427ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[4]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 5.838ns (logic 0.828ns (14.184%) route 5.010ns (85.816%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.064ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.253ns = ( 38.747 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.588ns
|
|
Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.286ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.561 5.237 U1/comptY
|
|
SLICE_X38Y49 FDRE r U1/comptY_reg[4]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.579 38.747 U1/CLK
|
|
SLICE_X38Y49 FDRE r U1/comptY_reg[4]/C
|
|
clock pessimism 0.588 39.335
|
|
clock uncertainty -0.147 39.188
|
|
SLICE_X38Y49 FDRE (Setup_fdre_C_R) -0.524 38.664 U1/comptY_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 38.664
|
|
arrival time -5.237
|
|
-------------------------------------------------------------------
|
|
slack 33.427
|
|
|
|
Slack (MET) : 33.613ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[1]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.286ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.147 39.057
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.628 U1/comptY_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 38.628
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.613
|
|
|
|
Slack (MET) : 33.613ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[2]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.286ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[2]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[2]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.147 39.057
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.628 U1/comptY_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 38.628
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.613
|
|
|
|
Slack (MET) : 33.613ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[7]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.286ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[7]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[7]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.147 39.057
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.628 U1/comptY_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 38.628
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.613
|
|
|
|
Slack (MET) : 33.613ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[8]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.286ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[8]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[8]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.147 39.057
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.628 U1/comptY_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 38.628
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.613
|
|
|
|
Slack (MET) : 33.613ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[9]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.286ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[9]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[9]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.147 39.057
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.628 U1/comptY_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 38.628
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.613
|
|
|
|
Slack (MET) : 33.756ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[6]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 5.472ns (logic 0.828ns (15.132%) route 4.644ns (84.868%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.286ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.196 4.871 U1/comptY
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.147 39.057
|
|
SLICE_X36Y50 FDRE (Setup_fdre_C_R) -0.429 38.628 U1/comptY_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 38.628
|
|
arrival time -4.871
|
|
-------------------------------------------------------------------
|
|
slack 33.756
|
|
|
|
Slack (MET) : 33.994ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[0]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 5.139ns (logic 0.828ns (16.112%) route 4.311ns (83.888%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.286ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 0.863 4.538 U1/comptY
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.147 39.057
|
|
SLICE_X38Y51 FDRE (Setup_fdre_C_R) -0.524 38.533 U1/comptY_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 38.533
|
|
arrival time -4.538
|
|
-------------------------------------------------------------------
|
|
slack 33.994
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.261ns (arrival time - required time)
|
|
Source: U1/comptY_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.368ns (logic 0.183ns (49.756%) route 0.185ns (50.244%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[1]/Q
|
|
net (fo=29, routed) 0.185 -0.148 U1/comptY_reg__0[1]
|
|
SLICE_X36Y51 LUT3 (Prop_lut3_I0_O) 0.042 -0.106 r U1/comptY[2]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.106 U1/comptY[2]_i_1_n_0
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[2]/C
|
|
clock pessimism 0.232 -0.474
|
|
SLICE_X36Y51 FDRE (Hold_fdre_C_D) 0.107 -0.367 U1/comptY_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.367
|
|
arrival time -0.106
|
|
-------------------------------------------------------------------
|
|
slack 0.261
|
|
|
|
Slack (MET) : 0.261ns (arrival time - required time)
|
|
Source: U1/comptX_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[5]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.353ns (logic 0.186ns (52.682%) route 0.167ns (47.318%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.705ns
|
|
Source Clock Delay (SCD): -0.473ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.588 -0.473 U1/CLK
|
|
SLICE_X43Y54 FDRE r U1/comptX_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X43Y54 FDRE (Prop_fdre_C_Q) 0.141 -0.332 r U1/comptX_reg[5]/Q
|
|
net (fo=25, routed) 0.167 -0.165 U1/comptX_reg__0[5]
|
|
SLICE_X43Y54 LUT6 (Prop_lut6_I5_O) 0.045 -0.120 r U1/comptX[5]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.120 U1/plusOp[5]
|
|
SLICE_X43Y54 FDRE r U1/comptX_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.858 -0.705 U1/CLK
|
|
SLICE_X43Y54 FDRE r U1/comptX_reg[5]/C
|
|
clock pessimism 0.232 -0.473
|
|
SLICE_X43Y54 FDRE (Hold_fdre_C_D) 0.092 -0.381 U1/comptX_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 0.381
|
|
arrival time -0.120
|
|
-------------------------------------------------------------------
|
|
slack 0.261
|
|
|
|
Slack (MET) : 0.280ns (arrival time - required time)
|
|
Source: U1/comptX_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[8]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.387ns (logic 0.183ns (47.319%) route 0.204ns (52.681%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q
|
|
net (fo=20, routed) 0.204 -0.129 U1/comptX_reg__0[7]
|
|
SLICE_X41Y57 LUT5 (Prop_lut5_I0_O) 0.042 -0.087 r U1/comptX[8]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.087 U1/plusOp[8]
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[8]/C
|
|
clock pessimism 0.232 -0.474
|
|
SLICE_X41Y57 FDRE (Hold_fdre_C_D) 0.107 -0.367 U1/comptX_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.367
|
|
arrival time -0.087
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (arrival time - required time)
|
|
Source: U1/comptY_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.371ns (logic 0.186ns (50.162%) route 0.185ns (49.838%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[1]/Q
|
|
net (fo=29, routed) 0.185 -0.148 U1/comptY_reg__0[1]
|
|
SLICE_X36Y51 LUT2 (Prop_lut2_I1_O) 0.045 -0.103 r U1/comptY[1]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.103 U1/comptY[1]_i_1_n_0
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C
|
|
clock pessimism 0.232 -0.474
|
|
SLICE_X36Y51 FDRE (Hold_fdre_C_D) 0.091 -0.383 U1/comptY_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.383
|
|
arrival time -0.103
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.288ns (arrival time - required time)
|
|
Source: U1/comptX_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.419ns (logic 0.207ns (49.431%) route 0.212ns (50.569%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.705ns
|
|
Source Clock Delay (SCD): -0.473ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.588 -0.473 U1/CLK
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X42Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.309 r U1/comptX_reg[0]/Q
|
|
net (fo=25, routed) 0.212 -0.097 U1/comptX_reg__0[0]
|
|
SLICE_X42Y55 LUT2 (Prop_lut2_I0_O) 0.043 -0.054 r U1/comptX[1]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.054 U1/plusOp[1]
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.858 -0.705 U1/CLK
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[1]/C
|
|
clock pessimism 0.232 -0.473
|
|
SLICE_X42Y55 FDRE (Hold_fdre_C_D) 0.131 -0.342 U1/comptX_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.342
|
|
arrival time -0.054
|
|
-------------------------------------------------------------------
|
|
slack 0.288
|
|
|
|
Slack (MET) : 0.289ns (arrival time - required time)
|
|
Source: U1/comptX_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[9]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.398ns (logic 0.186ns (46.766%) route 0.212ns (53.234%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.705ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.248ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q
|
|
net (fo=20, routed) 0.212 -0.121 U1/comptX_reg__0[7]
|
|
SLICE_X41Y56 LUT6 (Prop_lut6_I3_O) 0.045 -0.076 r U1/comptX[9]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.076 U1/plusOp[9]
|
|
SLICE_X41Y56 FDRE r U1/comptX_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.858 -0.705 U1/CLK
|
|
SLICE_X41Y56 FDRE r U1/comptX_reg[9]/C
|
|
clock pessimism 0.248 -0.457
|
|
SLICE_X41Y56 FDRE (Hold_fdre_C_D) 0.092 -0.365 U1/comptX_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 0.365
|
|
arrival time -0.076
|
|
-------------------------------------------------------------------
|
|
slack 0.289
|
|
|
|
Slack (MET) : 0.297ns (arrival time - required time)
|
|
Source: U1/comptY_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.402ns (logic 0.183ns (45.514%) route 0.219ns (54.486%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q
|
|
net (fo=21, routed) 0.219 -0.114 U1/comptY_reg__0[6]
|
|
SLICE_X36Y50 LUT3 (Prop_lut3_I2_O) 0.042 -0.072 r U1/comptY[6]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.072 U1/plusOp__0[6]
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C
|
|
clock pessimism 0.232 -0.474
|
|
SLICE_X36Y50 FDRE (Hold_fdre_C_D) 0.105 -0.369 U1/comptY_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 0.369
|
|
arrival time -0.072
|
|
-------------------------------------------------------------------
|
|
slack 0.297
|
|
|
|
Slack (MET) : 0.299ns (arrival time - required time)
|
|
Source: U1/comptX_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.390ns (logic 0.186ns (47.724%) route 0.204ns (52.276%))
|
|
Logic Levels: 1 (LUT4=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q
|
|
net (fo=20, routed) 0.204 -0.129 U1/comptX_reg__0[7]
|
|
SLICE_X41Y57 LUT4 (Prop_lut4_I3_O) 0.045 -0.084 r U1/comptX[7]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.084 U1/plusOp[7]
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C
|
|
clock pessimism 0.232 -0.474
|
|
SLICE_X41Y57 FDRE (Hold_fdre_C_D) 0.091 -0.383 U1/comptX_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 0.383
|
|
arrival time -0.084
|
|
-------------------------------------------------------------------
|
|
slack 0.299
|
|
|
|
Slack (MET) : 0.301ns (arrival time - required time)
|
|
Source: U1/comptY_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[0]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.421ns (logic 0.209ns (49.671%) route 0.212ns (50.329%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X38Y51 FDRE (Prop_fdre_C_Q) 0.164 -0.310 f U1/comptY_reg[0]/Q
|
|
net (fo=29, routed) 0.212 -0.098 U1/comptY_reg__0[0]
|
|
SLICE_X38Y51 LUT1 (Prop_lut1_I0_O) 0.045 -0.053 r U1/comptY[0]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.053 U1/comptY[0]_i_1_n_0
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C
|
|
clock pessimism 0.232 -0.474
|
|
SLICE_X38Y51 FDRE (Hold_fdre_C_D) 0.120 -0.354 U1/comptY_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.354
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.301
|
|
|
|
Slack (MET) : 0.301ns (arrival time - required time)
|
|
Source: U1/comptX_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[0]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.421ns (logic 0.209ns (49.671%) route 0.212ns (50.329%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.705ns
|
|
Source Clock Delay (SCD): -0.473ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.588 -0.473 U1/CLK
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X42Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.309 f U1/comptX_reg[0]/Q
|
|
net (fo=25, routed) 0.212 -0.097 U1/comptX_reg__0[0]
|
|
SLICE_X42Y55 LUT1 (Prop_lut1_I0_O) 0.045 -0.052 r U1/comptX[0]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.052 U1/plusOp[0]
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.858 -0.705 U1/CLK
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C
|
|
clock pessimism 0.232 -0.473
|
|
SLICE_X42Y55 FDRE (Hold_fdre_C_D) 0.120 -0.353 U1/comptX_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.353
|
|
arrival time -0.052
|
|
-------------------------------------------------------------------
|
|
slack 0.301
|
|
|
|
|
|
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: clk_out1_clk_wiz_1_1
|
|
Waveform(ns): { 0.000 20.000 }
|
|
Period(ns): 40.000
|
|
Sources: { U0/inst/mmcm_adv_inst/CLKOUT0 }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y16 U0/inst/clkout1_buf/I
|
|
Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKOUT0
|
|
Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X42Y55 U1/comptX_reg[0]/C
|
|
Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X41Y56 U1/comptX_reg[10]/C
|
|
Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X42Y55 U1/comptX_reg[1]/C
|
|
Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X43Y54 U1/comptX_reg[2]/C
|
|
Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X43Y54 U1/comptX_reg[3]/C
|
|
Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X41Y56 U1/comptX_reg[4]/C
|
|
Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X38Y51 U1/comptY_reg[0]/C
|
|
Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X36Y51 U1/comptY_reg[1]/C
|
|
Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKOUT0
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X42Y55 U1/comptX_reg[0]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X41Y56 U1/comptX_reg[10]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X42Y55 U1/comptX_reg[1]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X43Y54 U1/comptX_reg[2]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X43Y54 U1/comptX_reg[3]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X41Y56 U1/comptX_reg[4]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X38Y51 U1/comptY_reg[0]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X38Y51 U1/comptY_reg[0]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X36Y51 U1/comptY_reg[1]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X36Y51 U1/comptY_reg[1]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X42Y55 U1/comptX_reg[0]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X41Y56 U1/comptX_reg[10]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X42Y55 U1/comptX_reg[1]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X43Y54 U1/comptX_reg[2]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X43Y54 U1/comptX_reg[3]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X41Y56 U1/comptX_reg[4]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X38Y51 U1/comptY_reg[0]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X36Y51 U1/comptY_reg[1]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X36Y51 U1/comptY_reg[2]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X40Y49 U1/comptY_reg[3]/C
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: clkfbout_clk_wiz_1_1
|
|
To Clock: clkfbout_clk_wiz_1_1
|
|
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
PW : 0 Failing Endpoints, Worst Slack 37.845ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: clkfbout_clk_wiz_1_1
|
|
Waveform(ns): { 0.000 20.000 }
|
|
Period(ns): 40.000
|
|
Sources: { U0/inst/mmcm_adv_inst/CLKFBOUT }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y17 U0/inst/clkf_buf/I
|
|
Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBOUT
|
|
Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBIN
|
|
Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 40.000 60.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBIN
|
|
Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBOUT
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: clk_out1_clk_wiz_1_1
|
|
To Clock: clk_out1_clk_wiz_1
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 33.269ns, Total Violation 0.000ns
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.101ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 33.269ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[3]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 6.142ns (logic 0.828ns (13.480%) route 5.314ns (86.520%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: 0.000ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.252ns = ( 38.748 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.651ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.866 5.542 U1/comptY
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[3]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.580 38.748 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[3]/C
|
|
clock pessimism 0.651 39.399
|
|
clock uncertainty -0.160 39.239
|
|
SLICE_X40Y49 FDRE (Setup_fdre_C_R) -0.429 38.810 U1/comptY_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 38.810
|
|
arrival time -5.542
|
|
-------------------------------------------------------------------
|
|
slack 33.269
|
|
|
|
Slack (MET) : 33.269ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[5]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 6.142ns (logic 0.828ns (13.480%) route 5.314ns (86.520%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: 0.000ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.252ns = ( 38.748 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.651ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.866 5.542 U1/comptY
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.580 38.748 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
clock pessimism 0.651 39.399
|
|
clock uncertainty -0.160 39.239
|
|
SLICE_X40Y49 FDRE (Setup_fdre_C_R) -0.429 38.810 U1/comptY_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 38.810
|
|
arrival time -5.542
|
|
-------------------------------------------------------------------
|
|
slack 33.269
|
|
|
|
Slack (MET) : 33.414ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[4]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 5.838ns (logic 0.828ns (14.184%) route 5.010ns (85.816%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.064ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.253ns = ( 38.747 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.588ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.561 5.237 U1/comptY
|
|
SLICE_X38Y49 FDRE r U1/comptY_reg[4]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.579 38.747 U1/CLK
|
|
SLICE_X38Y49 FDRE r U1/comptY_reg[4]/C
|
|
clock pessimism 0.588 39.335
|
|
clock uncertainty -0.160 39.175
|
|
SLICE_X38Y49 FDRE (Setup_fdre_C_R) -0.524 38.651 U1/comptY_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 38.651
|
|
arrival time -5.237
|
|
-------------------------------------------------------------------
|
|
slack 33.414
|
|
|
|
Slack (MET) : 33.600ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[1]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 38.615
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.600
|
|
|
|
Slack (MET) : 33.600ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[2]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[2]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[2]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 38.615
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.600
|
|
|
|
Slack (MET) : 33.600ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[7]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[7]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[7]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 38.615
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.600
|
|
|
|
Slack (MET) : 33.600ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[8]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[8]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[8]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 38.615
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.600
|
|
|
|
Slack (MET) : 33.600ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[9]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[9]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[9]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 38.615
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.600
|
|
|
|
Slack (MET) : 33.744ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[6]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 5.472ns (logic 0.828ns (15.132%) route 4.644ns (84.868%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.196 4.871 U1/comptY
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X36Y50 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 38.615
|
|
arrival time -4.871
|
|
-------------------------------------------------------------------
|
|
slack 33.744
|
|
|
|
Slack (MET) : 33.981ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[0]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 5.139ns (logic 0.828ns (16.112%) route 4.311ns (83.888%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 0.863 4.538 U1/comptY
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X38Y51 FDRE (Setup_fdre_C_R) -0.524 38.520 U1/comptY_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 38.520
|
|
arrival time -4.538
|
|
-------------------------------------------------------------------
|
|
slack 33.981
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.101ns (arrival time - required time)
|
|
Source: U1/comptY_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.368ns (logic 0.183ns (49.756%) route 0.185ns (50.244%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[1]/Q
|
|
net (fo=29, routed) 0.185 -0.148 U1/comptY_reg__0[1]
|
|
SLICE_X36Y51 LUT3 (Prop_lut3_I0_O) 0.042 -0.106 r U1/comptY[2]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.106 U1/comptY[2]_i_1_n_0
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[2]/C
|
|
clock pessimism 0.232 -0.474
|
|
clock uncertainty 0.160 -0.313
|
|
SLICE_X36Y51 FDRE (Hold_fdre_C_D) 0.107 -0.206 U1/comptY_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.206
|
|
arrival time -0.106
|
|
-------------------------------------------------------------------
|
|
slack 0.101
|
|
|
|
Slack (MET) : 0.101ns (arrival time - required time)
|
|
Source: U1/comptX_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[5]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.353ns (logic 0.186ns (52.682%) route 0.167ns (47.318%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.705ns
|
|
Source Clock Delay (SCD): -0.473ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.588 -0.473 U1/CLK
|
|
SLICE_X43Y54 FDRE r U1/comptX_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X43Y54 FDRE (Prop_fdre_C_Q) 0.141 -0.332 r U1/comptX_reg[5]/Q
|
|
net (fo=25, routed) 0.167 -0.165 U1/comptX_reg__0[5]
|
|
SLICE_X43Y54 LUT6 (Prop_lut6_I5_O) 0.045 -0.120 r U1/comptX[5]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.120 U1/plusOp[5]
|
|
SLICE_X43Y54 FDRE r U1/comptX_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.858 -0.705 U1/CLK
|
|
SLICE_X43Y54 FDRE r U1/comptX_reg[5]/C
|
|
clock pessimism 0.232 -0.473
|
|
clock uncertainty 0.160 -0.312
|
|
SLICE_X43Y54 FDRE (Hold_fdre_C_D) 0.092 -0.220 U1/comptX_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 0.220
|
|
arrival time -0.120
|
|
-------------------------------------------------------------------
|
|
slack 0.101
|
|
|
|
Slack (MET) : 0.119ns (arrival time - required time)
|
|
Source: U1/comptX_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[8]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.387ns (logic 0.183ns (47.319%) route 0.204ns (52.681%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q
|
|
net (fo=20, routed) 0.204 -0.129 U1/comptX_reg__0[7]
|
|
SLICE_X41Y57 LUT5 (Prop_lut5_I0_O) 0.042 -0.087 r U1/comptX[8]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.087 U1/plusOp[8]
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[8]/C
|
|
clock pessimism 0.232 -0.474
|
|
clock uncertainty 0.160 -0.313
|
|
SLICE_X41Y57 FDRE (Hold_fdre_C_D) 0.107 -0.206 U1/comptX_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.206
|
|
arrival time -0.087
|
|
-------------------------------------------------------------------
|
|
slack 0.119
|
|
|
|
Slack (MET) : 0.120ns (arrival time - required time)
|
|
Source: U1/comptY_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.371ns (logic 0.186ns (50.162%) route 0.185ns (49.838%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[1]/Q
|
|
net (fo=29, routed) 0.185 -0.148 U1/comptY_reg__0[1]
|
|
SLICE_X36Y51 LUT2 (Prop_lut2_I1_O) 0.045 -0.103 r U1/comptY[1]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.103 U1/comptY[1]_i_1_n_0
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C
|
|
clock pessimism 0.232 -0.474
|
|
clock uncertainty 0.160 -0.313
|
|
SLICE_X36Y51 FDRE (Hold_fdre_C_D) 0.091 -0.222 U1/comptY_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.222
|
|
arrival time -0.103
|
|
-------------------------------------------------------------------
|
|
slack 0.120
|
|
|
|
Slack (MET) : 0.127ns (arrival time - required time)
|
|
Source: U1/comptX_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.419ns (logic 0.207ns (49.431%) route 0.212ns (50.569%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.705ns
|
|
Source Clock Delay (SCD): -0.473ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.588 -0.473 U1/CLK
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X42Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.309 r U1/comptX_reg[0]/Q
|
|
net (fo=25, routed) 0.212 -0.097 U1/comptX_reg__0[0]
|
|
SLICE_X42Y55 LUT2 (Prop_lut2_I0_O) 0.043 -0.054 r U1/comptX[1]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.054 U1/plusOp[1]
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.858 -0.705 U1/CLK
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[1]/C
|
|
clock pessimism 0.232 -0.473
|
|
clock uncertainty 0.160 -0.312
|
|
SLICE_X42Y55 FDRE (Hold_fdre_C_D) 0.131 -0.181 U1/comptX_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.181
|
|
arrival time -0.054
|
|
-------------------------------------------------------------------
|
|
slack 0.127
|
|
|
|
Slack (MET) : 0.128ns (arrival time - required time)
|
|
Source: U1/comptX_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[9]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.398ns (logic 0.186ns (46.766%) route 0.212ns (53.234%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.705ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.248ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q
|
|
net (fo=20, routed) 0.212 -0.121 U1/comptX_reg__0[7]
|
|
SLICE_X41Y56 LUT6 (Prop_lut6_I3_O) 0.045 -0.076 r U1/comptX[9]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.076 U1/plusOp[9]
|
|
SLICE_X41Y56 FDRE r U1/comptX_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.858 -0.705 U1/CLK
|
|
SLICE_X41Y56 FDRE r U1/comptX_reg[9]/C
|
|
clock pessimism 0.248 -0.457
|
|
clock uncertainty 0.160 -0.296
|
|
SLICE_X41Y56 FDRE (Hold_fdre_C_D) 0.092 -0.204 U1/comptX_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 0.204
|
|
arrival time -0.076
|
|
-------------------------------------------------------------------
|
|
slack 0.128
|
|
|
|
Slack (MET) : 0.137ns (arrival time - required time)
|
|
Source: U1/comptY_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.402ns (logic 0.183ns (45.514%) route 0.219ns (54.486%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q
|
|
net (fo=21, routed) 0.219 -0.114 U1/comptY_reg__0[6]
|
|
SLICE_X36Y50 LUT3 (Prop_lut3_I2_O) 0.042 -0.072 r U1/comptY[6]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.072 U1/plusOp__0[6]
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C
|
|
clock pessimism 0.232 -0.474
|
|
clock uncertainty 0.160 -0.313
|
|
SLICE_X36Y50 FDRE (Hold_fdre_C_D) 0.105 -0.208 U1/comptY_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 0.208
|
|
arrival time -0.072
|
|
-------------------------------------------------------------------
|
|
slack 0.137
|
|
|
|
Slack (MET) : 0.138ns (arrival time - required time)
|
|
Source: U1/comptX_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.390ns (logic 0.186ns (47.724%) route 0.204ns (52.276%))
|
|
Logic Levels: 1 (LUT4=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q
|
|
net (fo=20, routed) 0.204 -0.129 U1/comptX_reg__0[7]
|
|
SLICE_X41Y57 LUT4 (Prop_lut4_I3_O) 0.045 -0.084 r U1/comptX[7]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.084 U1/plusOp[7]
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C
|
|
clock pessimism 0.232 -0.474
|
|
clock uncertainty 0.160 -0.313
|
|
SLICE_X41Y57 FDRE (Hold_fdre_C_D) 0.091 -0.222 U1/comptX_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 0.222
|
|
arrival time -0.084
|
|
-------------------------------------------------------------------
|
|
slack 0.138
|
|
|
|
Slack (MET) : 0.140ns (arrival time - required time)
|
|
Source: U1/comptY_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[0]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.421ns (logic 0.209ns (49.671%) route 0.212ns (50.329%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X38Y51 FDRE (Prop_fdre_C_Q) 0.164 -0.310 f U1/comptY_reg[0]/Q
|
|
net (fo=29, routed) 0.212 -0.098 U1/comptY_reg__0[0]
|
|
SLICE_X38Y51 LUT1 (Prop_lut1_I0_O) 0.045 -0.053 r U1/comptY[0]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.053 U1/comptY[0]_i_1_n_0
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C
|
|
clock pessimism 0.232 -0.474
|
|
clock uncertainty 0.160 -0.313
|
|
SLICE_X38Y51 FDRE (Hold_fdre_C_D) 0.120 -0.193 U1/comptY_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.193
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.140
|
|
|
|
Slack (MET) : 0.140ns (arrival time - required time)
|
|
Source: U1/comptX_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[0]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns)
|
|
Data Path Delay: 0.421ns (logic 0.209ns (49.671%) route 0.212ns (50.329%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.705ns
|
|
Source Clock Delay (SCD): -0.473ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.588 -0.473 U1/CLK
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X42Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.309 f U1/comptX_reg[0]/Q
|
|
net (fo=25, routed) 0.212 -0.097 U1/comptX_reg__0[0]
|
|
SLICE_X42Y55 LUT1 (Prop_lut1_I0_O) 0.045 -0.052 r U1/comptX[0]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.052 U1/plusOp[0]
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.858 -0.705 U1/CLK
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C
|
|
clock pessimism 0.232 -0.473
|
|
clock uncertainty 0.160 -0.312
|
|
SLICE_X42Y55 FDRE (Hold_fdre_C_D) 0.120 -0.192 U1/comptX_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.192
|
|
arrival time -0.052
|
|
-------------------------------------------------------------------
|
|
slack 0.140
|
|
|
|
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: clk_out1_clk_wiz_1
|
|
To Clock: clk_out1_clk_wiz_1_1
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 33.269ns, Total Violation 0.000ns
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.101ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 33.269ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[3]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 6.142ns (logic 0.828ns (13.480%) route 5.314ns (86.520%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: 0.000ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.252ns = ( 38.748 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.651ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.866 5.542 U1/comptY
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[3]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.580 38.748 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[3]/C
|
|
clock pessimism 0.651 39.399
|
|
clock uncertainty -0.160 39.239
|
|
SLICE_X40Y49 FDRE (Setup_fdre_C_R) -0.429 38.810 U1/comptY_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 38.810
|
|
arrival time -5.542
|
|
-------------------------------------------------------------------
|
|
slack 33.269
|
|
|
|
Slack (MET) : 33.269ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[5]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 6.142ns (logic 0.828ns (13.480%) route 5.314ns (86.520%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: 0.000ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.252ns = ( 38.748 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.651ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.866 5.542 U1/comptY
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.580 38.748 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
clock pessimism 0.651 39.399
|
|
clock uncertainty -0.160 39.239
|
|
SLICE_X40Y49 FDRE (Setup_fdre_C_R) -0.429 38.810 U1/comptY_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 38.810
|
|
arrival time -5.542
|
|
-------------------------------------------------------------------
|
|
slack 33.269
|
|
|
|
Slack (MET) : 33.414ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[4]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 5.838ns (logic 0.828ns (14.184%) route 5.010ns (85.816%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.064ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.253ns = ( 38.747 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.588ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.561 5.237 U1/comptY
|
|
SLICE_X38Y49 FDRE r U1/comptY_reg[4]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.579 38.747 U1/CLK
|
|
SLICE_X38Y49 FDRE r U1/comptY_reg[4]/C
|
|
clock pessimism 0.588 39.335
|
|
clock uncertainty -0.160 39.175
|
|
SLICE_X38Y49 FDRE (Setup_fdre_C_R) -0.524 38.651 U1/comptY_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 38.651
|
|
arrival time -5.237
|
|
-------------------------------------------------------------------
|
|
slack 33.414
|
|
|
|
Slack (MET) : 33.600ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[1]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 38.615
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.600
|
|
|
|
Slack (MET) : 33.600ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[2]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[2]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[2]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 38.615
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.600
|
|
|
|
Slack (MET) : 33.600ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[7]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[7]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[7]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 38.615
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.600
|
|
|
|
Slack (MET) : 33.600ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[8]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[8]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[8]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 38.615
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.600
|
|
|
|
Slack (MET) : 33.600ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[9]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.340 5.015 U1/comptY
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[9]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[9]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 38.615
|
|
arrival time -5.015
|
|
-------------------------------------------------------------------
|
|
slack 33.600
|
|
|
|
Slack (MET) : 33.744ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[6]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 5.472ns (logic 0.828ns (15.132%) route 4.644ns (84.868%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 1.196 4.871 U1/comptY
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X36Y50 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 38.615
|
|
arrival time -4.871
|
|
-------------------------------------------------------------------
|
|
slack 33.744
|
|
|
|
Slack (MET) : 33.981ns (required time - arrival time)
|
|
Source: U1/comptY_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[0]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 5.139ns (logic 0.828ns (16.112%) route 4.311ns (83.888%))
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.195ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 )
|
|
Source Clock Delay (SCD): -0.601ns
|
|
Clock Pessimism Removal (CPR): 0.473ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.758 -0.601 U1/CLK
|
|
SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q
|
|
net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5]
|
|
SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O
|
|
net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0
|
|
SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O
|
|
net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0
|
|
SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O
|
|
net (fo=10, routed) 0.863 4.538 U1/comptY
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
40.000 40.000 r
|
|
L16 0.000 40.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 40.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 1.563 38.731 U1/CLK
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C
|
|
clock pessimism 0.473 39.204
|
|
clock uncertainty -0.160 39.044
|
|
SLICE_X38Y51 FDRE (Setup_fdre_C_R) -0.524 38.520 U1/comptY_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 38.520
|
|
arrival time -4.538
|
|
-------------------------------------------------------------------
|
|
slack 33.981
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.101ns (arrival time - required time)
|
|
Source: U1/comptY_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.368ns (logic 0.183ns (49.756%) route 0.185ns (50.244%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[1]/Q
|
|
net (fo=29, routed) 0.185 -0.148 U1/comptY_reg__0[1]
|
|
SLICE_X36Y51 LUT3 (Prop_lut3_I0_O) 0.042 -0.106 r U1/comptY[2]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.106 U1/comptY[2]_i_1_n_0
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[2]/C
|
|
clock pessimism 0.232 -0.474
|
|
clock uncertainty 0.160 -0.313
|
|
SLICE_X36Y51 FDRE (Hold_fdre_C_D) 0.107 -0.206 U1/comptY_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.206
|
|
arrival time -0.106
|
|
-------------------------------------------------------------------
|
|
slack 0.101
|
|
|
|
Slack (MET) : 0.101ns (arrival time - required time)
|
|
Source: U1/comptX_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[5]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.353ns (logic 0.186ns (52.682%) route 0.167ns (47.318%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.705ns
|
|
Source Clock Delay (SCD): -0.473ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.588 -0.473 U1/CLK
|
|
SLICE_X43Y54 FDRE r U1/comptX_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X43Y54 FDRE (Prop_fdre_C_Q) 0.141 -0.332 r U1/comptX_reg[5]/Q
|
|
net (fo=25, routed) 0.167 -0.165 U1/comptX_reg__0[5]
|
|
SLICE_X43Y54 LUT6 (Prop_lut6_I5_O) 0.045 -0.120 r U1/comptX[5]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.120 U1/plusOp[5]
|
|
SLICE_X43Y54 FDRE r U1/comptX_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.858 -0.705 U1/CLK
|
|
SLICE_X43Y54 FDRE r U1/comptX_reg[5]/C
|
|
clock pessimism 0.232 -0.473
|
|
clock uncertainty 0.160 -0.312
|
|
SLICE_X43Y54 FDRE (Hold_fdre_C_D) 0.092 -0.220 U1/comptX_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 0.220
|
|
arrival time -0.120
|
|
-------------------------------------------------------------------
|
|
slack 0.101
|
|
|
|
Slack (MET) : 0.119ns (arrival time - required time)
|
|
Source: U1/comptX_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[8]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.387ns (logic 0.183ns (47.319%) route 0.204ns (52.681%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q
|
|
net (fo=20, routed) 0.204 -0.129 U1/comptX_reg__0[7]
|
|
SLICE_X41Y57 LUT5 (Prop_lut5_I0_O) 0.042 -0.087 r U1/comptX[8]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.087 U1/plusOp[8]
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[8]/C
|
|
clock pessimism 0.232 -0.474
|
|
clock uncertainty 0.160 -0.313
|
|
SLICE_X41Y57 FDRE (Hold_fdre_C_D) 0.107 -0.206 U1/comptX_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.206
|
|
arrival time -0.087
|
|
-------------------------------------------------------------------
|
|
slack 0.119
|
|
|
|
Slack (MET) : 0.120ns (arrival time - required time)
|
|
Source: U1/comptY_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.371ns (logic 0.186ns (50.162%) route 0.185ns (49.838%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[1]/Q
|
|
net (fo=29, routed) 0.185 -0.148 U1/comptY_reg__0[1]
|
|
SLICE_X36Y51 LUT2 (Prop_lut2_I1_O) 0.045 -0.103 r U1/comptY[1]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.103 U1/comptY[1]_i_1_n_0
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C
|
|
clock pessimism 0.232 -0.474
|
|
clock uncertainty 0.160 -0.313
|
|
SLICE_X36Y51 FDRE (Hold_fdre_C_D) 0.091 -0.222 U1/comptY_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.222
|
|
arrival time -0.103
|
|
-------------------------------------------------------------------
|
|
slack 0.120
|
|
|
|
Slack (MET) : 0.127ns (arrival time - required time)
|
|
Source: U1/comptX_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.419ns (logic 0.207ns (49.431%) route 0.212ns (50.569%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.705ns
|
|
Source Clock Delay (SCD): -0.473ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.588 -0.473 U1/CLK
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X42Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.309 r U1/comptX_reg[0]/Q
|
|
net (fo=25, routed) 0.212 -0.097 U1/comptX_reg__0[0]
|
|
SLICE_X42Y55 LUT2 (Prop_lut2_I0_O) 0.043 -0.054 r U1/comptX[1]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.054 U1/plusOp[1]
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.858 -0.705 U1/CLK
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[1]/C
|
|
clock pessimism 0.232 -0.473
|
|
clock uncertainty 0.160 -0.312
|
|
SLICE_X42Y55 FDRE (Hold_fdre_C_D) 0.131 -0.181 U1/comptX_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.181
|
|
arrival time -0.054
|
|
-------------------------------------------------------------------
|
|
slack 0.127
|
|
|
|
Slack (MET) : 0.128ns (arrival time - required time)
|
|
Source: U1/comptX_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[9]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.398ns (logic 0.186ns (46.766%) route 0.212ns (53.234%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.705ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.248ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q
|
|
net (fo=20, routed) 0.212 -0.121 U1/comptX_reg__0[7]
|
|
SLICE_X41Y56 LUT6 (Prop_lut6_I3_O) 0.045 -0.076 r U1/comptX[9]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.076 U1/plusOp[9]
|
|
SLICE_X41Y56 FDRE r U1/comptX_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.858 -0.705 U1/CLK
|
|
SLICE_X41Y56 FDRE r U1/comptX_reg[9]/C
|
|
clock pessimism 0.248 -0.457
|
|
clock uncertainty 0.160 -0.296
|
|
SLICE_X41Y56 FDRE (Hold_fdre_C_D) 0.092 -0.204 U1/comptX_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 0.204
|
|
arrival time -0.076
|
|
-------------------------------------------------------------------
|
|
slack 0.128
|
|
|
|
Slack (MET) : 0.137ns (arrival time - required time)
|
|
Source: U1/comptY_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.402ns (logic 0.183ns (45.514%) route 0.219ns (54.486%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q
|
|
net (fo=21, routed) 0.219 -0.114 U1/comptY_reg__0[6]
|
|
SLICE_X36Y50 LUT3 (Prop_lut3_I2_O) 0.042 -0.072 r U1/comptY[6]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.072 U1/plusOp__0[6]
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C
|
|
clock pessimism 0.232 -0.474
|
|
clock uncertainty 0.160 -0.313
|
|
SLICE_X36Y50 FDRE (Hold_fdre_C_D) 0.105 -0.208 U1/comptY_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 0.208
|
|
arrival time -0.072
|
|
-------------------------------------------------------------------
|
|
slack 0.137
|
|
|
|
Slack (MET) : 0.138ns (arrival time - required time)
|
|
Source: U1/comptX_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.390ns (logic 0.186ns (47.724%) route 0.204ns (52.276%))
|
|
Logic Levels: 1 (LUT4=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q
|
|
net (fo=20, routed) 0.204 -0.129 U1/comptX_reg__0[7]
|
|
SLICE_X41Y57 LUT4 (Prop_lut4_I3_O) 0.045 -0.084 r U1/comptX[7]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.084 U1/plusOp[7]
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C
|
|
clock pessimism 0.232 -0.474
|
|
clock uncertainty 0.160 -0.313
|
|
SLICE_X41Y57 FDRE (Hold_fdre_C_D) 0.091 -0.222 U1/comptX_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 0.222
|
|
arrival time -0.084
|
|
-------------------------------------------------------------------
|
|
slack 0.138
|
|
|
|
Slack (MET) : 0.140ns (arrival time - required time)
|
|
Source: U1/comptY_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptY_reg[0]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.421ns (logic 0.209ns (49.671%) route 0.212ns (50.329%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.706ns
|
|
Source Clock Delay (SCD): -0.474ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.587 -0.474 U1/CLK
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X38Y51 FDRE (Prop_fdre_C_Q) 0.164 -0.310 f U1/comptY_reg[0]/Q
|
|
net (fo=29, routed) 0.212 -0.098 U1/comptY_reg__0[0]
|
|
SLICE_X38Y51 LUT1 (Prop_lut1_I0_O) 0.045 -0.053 r U1/comptY[0]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.053 U1/comptY[0]_i_1_n_0
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.857 -0.706 U1/CLK
|
|
SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C
|
|
clock pessimism 0.232 -0.474
|
|
clock uncertainty 0.160 -0.313
|
|
SLICE_X38Y51 FDRE (Hold_fdre_C_D) 0.120 -0.193 U1/comptY_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.193
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.140
|
|
|
|
Slack (MET) : 0.140ns (arrival time - required time)
|
|
Source: U1/comptX_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: U1/comptX_reg[0]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: clk_out1_clk_wiz_1_1
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns)
|
|
Data Path Delay: 0.421ns (logic 0.209ns (49.671%) route 0.212ns (50.329%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.705ns
|
|
Source Clock Delay (SCD): -0.473ns
|
|
Clock Pessimism Removal (CPR): -0.232ns
|
|
Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.313ns
|
|
Phase Error (PE): 0.000ns
|
|
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.588 -0.473 U1/CLK
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X42Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.309 f U1/comptX_reg[0]/Q
|
|
net (fo=25, routed) 0.212 -0.097 U1/comptX_reg__0[0]
|
|
SLICE_X42Y55 LUT1 (Prop_lut1_I0_O) 0.045 -0.052 r U1/comptX[0]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.052 U1/plusOp[0]
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_1_1 rise edge)
|
|
0.000 0.000 r
|
|
L16 0.000 0.000 r H125MHz (IN)
|
|
net (fo=0) 0.000 0.000 U0/inst/clk_in1
|
|
L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1
|
|
MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O
|
|
net (fo=21, routed) 0.858 -0.705 U1/CLK
|
|
SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C
|
|
clock pessimism 0.232 -0.473
|
|
clock uncertainty 0.160 -0.312
|
|
SLICE_X42Y55 FDRE (Hold_fdre_C_D) 0.120 -0.192 U1/comptX_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.192
|
|
arrival time -0.052
|
|
-------------------------------------------------------------------
|
|
slack 0.140
|
|
|
|
|
|
|
|
|
|
|