154 lines
7.1 KiB
XML
154 lines
7.1 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<GenRun Id="synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1641894418">
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<File Type="VDS-TIMING-PB" Name="VGA_top_timing_summary_synth.pb"/>
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<File Type="VDS-TIMINGSUMMARY" Name="VGA_top_timing_summary_synth.rpt"/>
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<File Type="RDS-DCP" Name="VGA_top.dcp"/>
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<File Type="RDS-UTIL-PB" Name="VGA_top_utilization_synth.pb"/>
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<File Type="RDS-UTIL" Name="VGA_top_utilization_synth.rpt"/>
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<File Type="RDS-PROPCONSTRS" Name="VGA_top_drc_synth.rpt"/>
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<File Type="RDS-RDS" Name="VGA_top.vds"/>
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<File Type="REPORTS-TCL" Name="VGA_top_reports.tcl"/>
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<File Type="PA-TCL" Name="VGA_top.tcl"/>
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<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
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<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/sources_1/imports/projet-electronique-clean/sources_snake/Diviseur.vhd">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../projet-electronique-clean/sources_snake/Diviseur.vhd"/>
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<Attr Name="ImportTime" Val="1641893383"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/imports/projet-electronique-clean/sources_snake/types.vhd">
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<FileInfo>
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<Attr Name="Library" Val="ourTypes"/>
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<Attr Name="ImportPath" Val="$PPRDIR/../../projet-electronique-clean/sources_snake/types.vhd"/>
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<Attr Name="ImportTime" Val="1641893383"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/imports/projet-electronique-clean/sources_snake/GeneRGB_V1.vhd">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../projet-electronique-clean/sources_snake/GeneRGB_V1.vhd"/>
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<Attr Name="ImportTime" Val="1641893383"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/imports/projet-electronique-clean/sources_snake/GeneSync.vhd">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../projet-electronique-clean/sources_snake/GeneSync.vhd"/>
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<Attr Name="ImportTime" Val="1641893383"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/imports/projet-electronique-clean/sources_snake/Gene_Snake.vhd">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../projet-electronique-clean/sources_snake/Gene_Snake.vhd"/>
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<Attr Name="ImportTime" Val="1641893383"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/imports/projet-electronique-clean/sources_snake/pomme.vhd">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../projet-electronique-clean/sources_snake/pomme.vhd"/>
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<Attr Name="ImportTime" Val="1641893383"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/imports/projet-electronique-clean/sources_snake/updateSnake.vhd">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../projet-electronique-clean/sources_snake/updateSnake.vhd"/>
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<Attr Name="ImportTime" Val="1641893383"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/imports/projet-electronique-clean/sources_snake/RAMController.vhd">
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<FileInfo SFType="VHDL2008">
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<Attr Name="ImportPath" Val="$PPRDIR/../../projet-electronique-clean/sources_snake/RAMController.vhd"/>
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<Attr Name="ImportTime" Val="1641893383"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/imports/projet-electronique-clean/sources_snake/snakeRam.vhd">
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<FileInfo SFType="VHDL2008">
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<Attr Name="ImportPath" Val="$PPRDIR/../../projet-electronique-clean/sources_snake/snakeRam.vhd"/>
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<Attr Name="ImportTime" Val="1641893383"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/imports/projet-electronique-clean/sources_snake/spritesRom.vhd">
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<FileInfo SFType="VHDL2008">
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<Attr Name="ImportPath" Val="$PPRDIR/../../projet-electronique-clean/sources_snake/spritesRom.vhd"/>
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<Attr Name="ImportTime" Val="1641893383"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/imports/projet-electronique-clean/sources_snake/VGA_top.vhd">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../projet-electronique-clean/sources_snake/VGA_top.vhd"/>
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<Attr Name="ImportTime" Val="1641894412"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/imports/projet-electronique-clean/sprites/pomme.mem">
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<FileInfo>
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<Attr Name="UserDisabled" Val="1"/>
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<Attr Name="ImportPath" Val="$PPRDIR/../../projet-electronique-clean/sprites/pomme.mem"/>
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<Attr Name="ImportTime" Val="1641893383"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/imports/projet-electronique-clean/sprites/sprites.mem">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../projet-electronique-clean/sprites/sprites.mem"/>
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<Attr Name="ImportTime" Val="1641893383"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="VGA_top"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
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<Filter Type="Constrs"/>
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<File Path="$PSRCDIR/constrs_1/imports/sources_snake/ZYBO_Master.xdc">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../projet-electronique-clean/sources_snake/ZYBO_Master.xdc"/>
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<Attr Name="ImportTime" Val="1641893383"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="ConstrsType" Val="XDC"/>
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</Config>
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</FileSet>
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<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
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<Filter Type="Utils"/>
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<Config>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
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<Desc>Vivado Synthesis Defaults</Desc>
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</StratHandle>
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<Step Id="synth_design"/>
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</Strategy>
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<BlockFileSet Type="BlockSrcs" Name="clk_wiz_0"/>
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</GenRun>
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