46 lines
2.4 KiB
Plaintext
46 lines
2.4 KiB
Plaintext
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
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| Date : Tue Dec 7 12:43:47 2021
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| Host : irb121-02-w running 64-bit major release (build 9200)
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| Command : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
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| Design : VGA_top
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| Device : xc7z010clg400-1
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| Speed File : -1
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| Design State : Fully Routed
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Report Methodology
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Table of Contents
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-----------------
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1. REPORT SUMMARY
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2. REPORT DETAILS
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1. REPORT SUMMARY
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-----------------
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Netlist: netlist
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Floorplan: design_1
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Design limits: <entire design considered>
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Max violations: <unlimited>
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Violations found: 2
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+----------+----------+------------------------------------------------+------------+
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| Rule | Severity | Description | Violations |
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+----------+----------+------------------------------------------------+------------+
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| TIMING-6 | Warning | No common primary clock between related clocks | 2 |
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+----------+----------+------------------------------------------------+------------+
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2. REPORT DETAILS
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-----------------
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TIMING-6#1 Warning
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No common primary clock between related clocks
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The clocks clk_out1_clk_wiz_1 and clk_out1_clk_wiz_1_1 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_out1_clk_wiz_1] -to [get_clocks clk_out1_clk_wiz_1_1]
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Related violations: <none>
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TIMING-6#2 Warning
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No common primary clock between related clocks
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The clocks clk_out1_clk_wiz_1_1 and clk_out1_clk_wiz_1 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_out1_clk_wiz_1_1] -to [get_clocks clk_out1_clk_wiz_1]
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Related violations: <none>
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