131 lines
4.4 KiB
VHDL
131 lines
4.4 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12/15/2021 02:06:27 PM
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-- Design Name:
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-- Module Name: updateSnake - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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library ourTypes;
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use ourTypes.types.all;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity updateSnake is
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generic ( dataSize : integer);
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Port (
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clk_lente : in std_logic;
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clk_rapide : in std_logic;
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reset : in std_logic;
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address : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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dataIn : in std_logic_vector(dataSize-1 downto 0);
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dataOut : out std_logic_vector(dataSize-1 downto 0);
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writeEnable : out std_logic := '1';
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matAddress : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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matDataIn : inout std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
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matDataOut : out std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
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matWriteEnable : out std_logic := '1'
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);
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end updateSnake;
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architecture Behavioral of updateSnake is
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signal index : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := to_unsigned(0,SNAKE_ADDRESS_SIZE);
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signal currentSnake : pos;
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signal update: std_logic := '0';
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signal isUpdating: std_logic := '0';
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signal updateIndex : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
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signal state : unsigned(3 downto 0) := (others => '0');
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begin
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process(currentSnake, updateIndex, update, clk_rapide, clk_lente,reset,index) --process de reset
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variable cSnake : pos;
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begin
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if rising_edge(clk_lente) then
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isUpdating <= '1';
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updateIndex <= to_unsigned(0,SNAKE_ADDRESS_SIZE);
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end if;
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if(clk_rapide'event and clk_rapide = '1') then
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if(reset = '0') then --il faut qu'on ai le reset sur la clk car il controle indirectement l'entrée de la RAM
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index <= to_unsigned(0,SNAKE_ADDRESS_SIZE);
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writeEnable <= '1';
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matWriteEnable <= '1';
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update <= '0';
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else
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index <= index + 1;
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if(index = MAX_SNAKE-1) then
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index <= to_unsigned(0,SNAKE_ADDRESS_SIZE);
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writeEnable <= '0';
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matWriteEnable <= '0';
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update <= '1';
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end if;
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end if;
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if(update = '1' and isUpdating = '1') then
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state <= state + 1;
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if(state = 0) then
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writeEnable <= '0';
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elsif(state = 1) then
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cSnake := to_pos(dataIn);
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cSnake.X := to_unsigned(to_integer(cSnake.X) + to_integer(cSnake.dirX),10);
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cSnake.Y := to_unsigned(to_integer(cSnake.Y) + to_integer(cSnake.dirY),9);
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dataOut <= to_stdlogicvector(cSnake);
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writeEnable <= '1';
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elsif(state = 2) then
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writeEnable <= '0';
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updateIndex <= updateIndex + 1;
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state <= to_unsigned(0,4);
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end if;
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if(updateIndex = MAX_SNAKE-1) then
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isUpdating <= '0';
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end if;
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address <= updateIndex;
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end if;
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end if;
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if update = '0' then
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dataOut <= to_stdlogicvector(currentSnake);
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if(index < 13) then
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currentSnake.X <= to_unsigned(8+to_integer(index)*16,10);
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currentSnake.Y <= to_unsigned(8,9);
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currentSnake.dirX <= to_signed(-1,2);
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currentSnake.dirY <= to_signed(0,2);
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currentSnake.isDefined <= '1';
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else
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currentSnake.X <= to_unsigned(8,10);
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currentSnake.Y <= to_unsigned(8,9);
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currentSnake.dirX <= to_signed(0,2);
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currentSnake.dirY <= to_signed(1,2);
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currentSnake.isDefined <= '0';
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end if;
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matAddress <= to_unsigned(to_integer(index),SNAKE_ADDRESS_SIZE);
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matDataOut <= std_logic_vector(to_unsigned(to_integer(index),SNAKE_ADDRESS_SIZE));
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address <= index;
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end if;
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end process;
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end Behavioral;
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