308 lines
8.5 KiB
VHDL
308 lines
8.5 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 19.10.2017 08:01:54
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-- Design Name:
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-- Module Name: VGA_top - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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library ourTypes;
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use ourTypes.types.all;
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entity VGA_top is
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Port ( H125MHz : in STD_LOGIC;
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resetGeneral : in std_logic;
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led : out std_logic_vector (3 downto 0);
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vga_hs : out STD_LOGIC;
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vga_vs : out STD_LOGIC;
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vga_r : out STD_LOGIC_VECTOR (4 downto 0);
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vga_g : out STD_LOGIC_VECTOR (5 downto 0);
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vga_b : out STD_LOGIC_VECTOR (4 downto 0));
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end VGA_top;
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architecture Behavioral of VGA_top is
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component clk_wiz_0
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port
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(-- Clock in ports
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clk_in1 : in std_logic;
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-- Clock out ports
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clk_out1 : out std_logic
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);
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end component;
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ATTRIBUTE SYN_BLACK_BOX : BOOLEAN;
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ATTRIBUTE SYN_BLACK_BOX OF clk_wiz_0 : COMPONENT IS TRUE;
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ATTRIBUTE BLACK_BOX_PAD_PIN : STRING;
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ATTRIBUTE BLACK_BOX_PAD_PIN OF clk_wiz_0 : COMPONENT IS "clk_in1,clk_out1";
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component GeneSync is
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Port ( CLK : in std_logic;
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HSYNC : out std_logic;
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VSYNC : out std_logic;
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IMG : out std_logic;
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X : out std_logic_vector(9 downto 0);
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Y : out std_logic_vector(8 downto 0));
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end component;
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component GeneRGB_V1 is
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Port (
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X : in unsigned(9 downto 0);
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Y : in unsigned(8 downto 0);
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IMG : in std_logic;
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R : out std_logic_vector(4 downto 0);
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G : out std_logic_vector(5 downto 0);
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B : out std_logic_vector(4 downto 0);
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snakeIn : in color);
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end component;
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component Gene_Snake
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generic ( addressSize : integer:=SNAKE_ADDRESS_SIZE);
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Port ( X : in unsigned (9 downto 0);
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Y : in unsigned (8 downto 0);
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clk: in std_logic;
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reset: in std_logic;
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currentSnake : in pos;
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updateOrder : in std_logic;
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listRef : in unsigned(addressSize-1 downto 0);
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colorOut : out color;
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currentAddress : out unsigned(addressSize-1 downto 0);
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matAddress : out unsigned(addressSize-1 downto 0);
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ROMAddress : out unsigned(SPRITES_ADDRESS_SIZE-1 downto 0);
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ROMData : in std_logic_vector(SPRITES_DATA_SIZE-1 downto 0)
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);
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end component Gene_Snake;
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signal dummyPos : pos; --juste pour avoir la taille du type
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component updateSnake
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generic ( dataSize : integer := to_stdlogicvector(dummyPos)'length);
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Port (
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clk : in std_logic;
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reset : in std_logic;
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address : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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data : out std_logic_vector(dataSize-1 downto 0);
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writeEnable : out std_logic;
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matAddress : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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matData : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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matWriteEnable : out std_logic
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);
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end component updateSnake;
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component snakeRam
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generic (length : integer;
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addressSize : integer;
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dataSize : integer
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);
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Port ( address1 : in unsigned(addressSize-1 downto 0);
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data1 : out std_logic_vector(dataSize-1 downto 0);
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writeEnable1 : in STD_LOGIC;
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clk1 : in STD_LOGIC;
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address2 : in unsigned(addressSize-1 downto 0);
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data2 : in std_logic_vector(dataSize-1 downto 0);
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writeEnable2 : in STD_LOGIC;
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clk2 : in STD_LOGIC);
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end component snakeRam;
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component spritesRom
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generic( addressSize : integer := SPRITES_ADDRESS_SIZE;
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length : integer := SPRITES_DATA_LENGTH;
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dataSize : integer := SPRITES_DATA_SIZE;
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fileName : string := "../projet-electronique/sprites/sprites.mem"
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);
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Port ( address : in unsigned (addressSize-1 downto 0);
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data : out STD_LOGIC_VECTOR (dataSize-1 downto 0);
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clk : in STD_LOGIC);
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end component spritesRom;
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component Diviseur
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generic (nbBits : integer:=8);
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Port ( clk_in : in STD_LOGIC;
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reset : in STD_LOGIC;
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max : in unsigned (nbBits-1 downto 0);
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clk_out : out STD_LOGIC);
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end component Diviseur;
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signal Xi : std_logic_vector(9 downto 0);
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signal Yi : std_logic_vector(8 downto 0);
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signal Xpxl : unsigned(9 downto 0);
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signal Ypxl : unsigned(8 downto 0);
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signal IMGi : std_logic;
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signal pxl_clk : std_logic;
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signal clk_lente: std_logic;
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signal valPosX: unsigned (9 downto 0);
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signal valPosY: unsigned (8 downto 0);
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signal snakeColor: color;
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signal displayRAMAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal displayRAMData : std_logic_vector(to_stdlogicvector(dummyPos)'length-1 downto 0);
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signal updateRAMAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal updateRAMData : std_logic_vector(to_stdlogicvector(dummyPos)'length-1 downto 0);
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signal updateRAMWE : std_logic;
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signal matdispRAMAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal matdispRAMData : std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal matupdRAMAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal matupdRAMData : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
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signal matupdRAMWE : std_logic;
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signal spritesROMAddress : unsigned(SPRITES_ADDRESS_SIZE-1 downto 0);
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signal spritesROMData : std_logic_vector(SPRITES_DATA_SIZE-1 downto 0);
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signal clk_latch : std_logic;
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begin
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Xpxl <= unsigned(Xi);
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Ypxl <= unsigned(Yi);
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U0 : clk_wiz_0
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port map (
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-- Clock in ports
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clk_in1 => H125MHz,
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-- Clock out ports
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clk_out1 => pxl_clk
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);
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U1 : GeneSync
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port map(
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CLK => pxl_clk,
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HSYNC => vga_hs,
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VSYNC => vga_vs,
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IMG => IMGi,
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X => Xi,
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Y => Yi);
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U2 : GeneRGB_V1
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port map(
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X => Xpxl,
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Y => Ypxl,
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IMG => IMGi,
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R => vga_r,
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G => vga_g,
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B => vga_b,
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snakeIn => snakeColor);
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U3 : Diviseur
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-- pxl_clock 25MHz, clk_lente ~60Hz, 1 coup sur clk_lente = 25e6/60 = 4.2e5 coups sur pxl_clk. ln(4.2e5)/ln(2)=18.6, donc on prend 19bits
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generic map (nbBits => 19)
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port map (
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clk_in => pxl_clk,
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reset => resetGeneral,
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max => to_unsigned(420000,19),
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clk_out => clk_lente
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);
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U4 : Gene_Snake
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port map (
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X => Xpxl,
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Y => Ypxl,
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clk => H125Mhz,
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reset => resetGeneral,
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currentSnake => to_pos(displayRamData),
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updateOrder => pxl_clk,
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listRef => unsigned(matdispRAMData),
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colorOut => snakeColor,
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currentAddress => displayRamAddress,
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matAddress => matdispRAMAddress,
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ROMAddress => spritesROMAddress,
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ROMData => spritesROMData
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);
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U5 : updateSnake
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port map (
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clk => H125MHz,
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reset => resetGeneral,
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address => updateRAMAddress,
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data => updateRAMData,
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writeEnable => updateRAMWE,
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matAddress => matupdRAMAddress,
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matData => matupdRAMData,
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matWriteEnable => matupdRAMWE
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);
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U6 : snakeRAM --La RAM pour le snake
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generic map (
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length => MAX_SNAKE,
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addressSize => SNAKE_ADDRESS_SIZE,
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dataSize => to_stdlogicvector(dummyPos)'length
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)
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port map (
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address1 => displayRAMAddress,
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data1 => displayRAMdata,
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writeEnable1 => '0',
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clk1 => H125MHz,
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address2 => updateRAMAddress,
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data2 => updateRAMData,
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writeEnable2 => updateRAMWE,
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clk2 => H125MHz
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);
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U7 : snakeRAM --La RAM pour la matrice de correspondance
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generic map (
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length => MAX_SNAKE,
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addressSize => SNAKE_ADDRESS_SIZE,
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dataSize => SNAKE_ADDRESS_SIZE
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)
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port map (
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address1 => matdispRAMAddress,
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data1 => matdispRAMdata,
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writeEnable1 => '0',
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clk1 => H125MHz,
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address2 => matupdRAMAddress,
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data2 => std_logic_vector(matupdRAMData),
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writeEnable2 => matupdRAMWE,
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clk2 => H125MHz
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);
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U8 : spritesROM
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port map(
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address => spritesROMAddress,
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data => spritesROMData,
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clk => H125MHz
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);
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led(0) <= resetGeneral;
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led(1) <= updateRAMWE;
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end Behavioral;
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