snake-vhdl/sources_snake/snakeRam.vhd

79 lines
2.0 KiB
VHDL

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/16/2021 09:57:33 PM
-- Design Name:
-- Module Name: snakeRam - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
library ourTypes;
use ourTypes.types.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity snakeRam is
generic (
length : integer;
addressSize : integer;
dataSize : integer
);
Port ( address1 : in unsigned(addressSize-1 downto 0);
data1 : out std_logic_vector(dataSize-1 downto 0);
writeEnable1 : in STD_LOGIC;
clk1 : in STD_LOGIC;
address2 : in unsigned(addressSize-1 downto 0);
data2 : in std_logic_vector(dataSize-1 downto 0);
writeEnable2 : in STD_LOGIC;
clk2 : in STD_LOGIC);
end snakeRam;
architecture Behavioral of snakeRam is
type listData is array(0 to length-1) of std_logic_vector(dataSize-1 downto 0);
signal mem : listData;
begin
process(clk1,address1)
begin
if(clk1'event and clk1 = '1') then
data1 <= mem(to_integer(address1));
-- if(writeEnable1 = '1') then
-- mem(to_integer(address1)) <= data1;
-- end if;
end if;
end process;
process(clk2,address2,data2)
begin
if(clk2'event and clk2 = '1') then
-- data2 <= mem(to_integer(address2));
if(writeEnable2 = '1') then
mem(to_integer(address2)) <= data2;
end if;
end if;
end process;
end Behavioral;