72 lines
1.8 KiB
VHDL
72 lines
1.8 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12/21/2021 03:36:18 PM
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-- Design Name:
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-- Module Name: spritesRom - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use std.textio.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity spritesRom is
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generic( addressSize : integer;
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length : integer;
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dataSize : integer;
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fileName : string
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);
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Port ( address : in unsigned (addressSize-1 downto 0);
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data : out STD_LOGIC_VECTOR (dataSize-1 downto 0);
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clk : in STD_LOGIC);
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end spritesRom;
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architecture Behavioral of spritesRom is
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type listData is array(0 to length-1) of std_logic_vector(dataSize-1 downto 0);
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--code "emprunté" ici : https://vhdlwhiz.com/initialize-ram-from-file/
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impure function init_ram_hex return listData is
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file text_file : text open read_mode is fileName;
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variable text_line : line;
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variable ram_content : listData;
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begin
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for i in 0 to length-1 loop
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readline(text_file, text_line);
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hread(text_line, ram_content(i));
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end loop;
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return ram_content;
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end function;
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signal mem : listData := init_ram_hex;
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begin
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process(clk,address)
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begin
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if(clk'event and clk = '1') then
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data <= mem(TO_INTEGER(address));
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end if;
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end process;
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end Behavioral; |