nbBit mux

ReceptionTrame_lib/receptionTrame_op.vhd

@@ -46,6 +46,7 @@ SIGNAL octetRecu_int : std_logic_vector(7 downto 0);
 SIGNAL nbDataField_INIT_int : integer := 0;
 SIGNAL nbDataField_INIT : unsigned(2 downto 0);
 SIGNAL n_INIT : unsigned(n_WIDTH - 1 downto 0);
+SIGNAL nbBit_INIT : unsigned(3 downto 0);
 
 COMPONENT D_FF
   PORT(
@@ -186,4 +187,11 @@ N_cmp : counter
     val => OPEN,
     max => n_0
   );
+
+-- NbBit mux
+with nbBit_SELECT SELECT
+  nbBit_INIT <= 
+    to_unsigned(13, 4) when '0',
+    to_unsigned(8, 4) when '1',
+    to_unsigned(0, 4) when others;
 END ARCHITECTURE arch;