nbBit mux
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@ -46,6 +46,7 @@ SIGNAL octetRecu_int : std_logic_vector(7 downto 0);
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SIGNAL nbDataField_INIT_int : integer := 0;
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SIGNAL nbDataField_INIT_int : integer := 0;
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SIGNAL nbDataField_INIT : unsigned(2 downto 0);
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SIGNAL nbDataField_INIT : unsigned(2 downto 0);
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SIGNAL n_INIT : unsigned(n_WIDTH - 1 downto 0);
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SIGNAL n_INIT : unsigned(n_WIDTH - 1 downto 0);
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SIGNAL nbBit_INIT : unsigned(3 downto 0);
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COMPONENT D_FF
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COMPONENT D_FF
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PORT(
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PORT(
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@ -186,4 +187,11 @@ N_cmp : counter
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val => OPEN,
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val => OPEN,
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max => n_0
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max => n_0
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);
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);
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-- NbBit mux
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with nbBit_SELECT SELECT
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nbBit_INIT <=
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to_unsigned(13, 4) when '0',
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to_unsigned(8, 4) when '1',
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to_unsigned(0, 4) when others;
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END ARCHITECTURE arch;
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END ARCHITECTURE arch;
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