shift register

STDLIB_lib/STDLIB_lib.core

@@ -7,6 +7,7 @@ filesets:
     files:
       - D_FF.vhd
       - D_FF_bank.vhd
+      - shift_register.vhd
     file_type: vhdlSource
 
   tb:

STDLIB_lib/shift_register.vhd

@@ -0,0 +1,33 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY shift_register IS
+  GENERIC(
+    WIDTH: integer
+  );
+  PORT(
+    H: IN std_logic;
+    H_EN: IN std_logic;
+    nRst : IN std_logic;
+    D: IN std_logic;
+    Q: OUT std_logic_vector
+  );
+END shift_register;
+
+ARCHITECTURE arch of shift_register IS
+SIGNAL data : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
+BEGIN
+
+Q <= data;
+
+sr: PROCESS(H, nRst)
+BEGIN
+  if(nRst = '0') THEN
+    data <= (others => '0');
+  ELSIF(rising_edge(H)) THEN
+    data <= data(WIDTH-2 downto 0) & D;
+  END IF;
+END PROCESS sr;
+
+END ARCHITECTURE arch;

STDLIB_lib/stdlib_tb.vhd

@@ -19,6 +19,10 @@ SIGNAL D_FFb_D : std_logic_vector(7 downto 0);
 SIGNAL D_FFb_Rst : std_logic;
 SIGNAL D_FFb_Q : std_logic_vector(7 downto 0);
 
+SIGNAL SR_D : std_logic;
+SIGNAL SR_Rst : std_logic;
+SIGNAL SR_Q : std_logic_vector(7 downto 0);
+
 COMPONENT D_FF
   PORT(
     H: IN std_logic;
@@ -37,6 +41,19 @@ COMPONENT D_FF_BANK
   );
 END COMPONENT;
 
+COMPONENT shift_register
+  GENERIC(
+    WIDTH: integer
+  );
+  PORT(
+    H: IN std_logic;
+    H_EN: IN std_logic;
+    nRst : IN std_logic;
+    D: IN std_logic;
+    Q: OUT std_logic_vector
+  );
+END COMPONENT;
+
 BEGIN
 
 CLK_gen : PROCESS
@@ -85,6 +102,24 @@ BEGIN
   assert D_FFb_Q = "00000000" report "D_FF_bank reset error" severity error;
 END PROCESS D_FFb_test;
 
+SR_test : PROCESS
+BEGIN
+  SR_Rst <= '0';
+  SR_D <= '1';
+
+  WAIT UNTIL CLK = '1';
+  SR_Rst <= '1';
+  for i in SR_Q'RANGE loop
+    SR_D <= not SR_D;
+    WAIT UNTIL CLK = '1';
+  end loop;
+  WAIT UNTIL CLK = '1';
+  assert SR_Q = "01010101" report "shift register wrong output" severity error;
+  SR_Rst <= '0';
+
+  WAIT UNTIL CLK = '0';
+  assert SR_Q = "00000000" report "shft register reset error" severity error;
+END PROCESS SR_test;
 
 U0 : D_FF
   PORT MAP (
@@ -94,11 +129,24 @@ U0 : D_FF
     Q => D_FF_Q
   );
 
-U1 : D_FF_BANK PORT MAP(
+U1 : D_FF_BANK
+  PORT MAP(
     H => CLK,
     D => D_FFb_D,
     nRst => D_FFb_Rst,
     Q => D_FFb_Q
-);
+  );
+
+U2 : shift_register
+  GENERIC MAP(
+    WIDTH => SR_Q'LENGTH
+  )
+  PORT MAP(
+    H => CLK,
+    H_EN => '1',
+    nRst => SR_Rst,
+    D => SR_D,
+    Q => SR_Q
+  );
 
 END ARCHITECTURE arch;