serial->para

ReceptionTrame_lib/ReceptionTrame.core

@@ -7,9 +7,12 @@ filesets:
     files:
       - receptionTrame_op.vhd
     file_type: vhdlSource
+    depend:
+      - ETN4:STDLIB:STDLIB:1.0.0
 
   tb:
     files:
+      - receptionTrame_tb.vhd
     file_type: vhdlSource
 
 

ReceptionTrame_lib/receptionTrame_op.vhd

@@ -2,14 +2,16 @@ LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 USE ieee.std_logic_arith.all;
 
-ENTITY receptionTrame IS
+ENTITY receptionTrame_op IS
   GENERIC(
-    N: integer := 1200;
+    N: integer := 1200
   );
   PORT(
-    H: IN std_logic; 
+    H: IN std_logic;
     nCLR: IN std_logic;
     Lin: IN std_logic;
+
+    octetRecu_EN : IN std_logic;
     
     n_SELECT: IN std_logic;
     n_LOAD: IN std_logic;
@@ -31,25 +33,59 @@ ENTITY receptionTrame IS
     nbData_0: OUT std_logic;
 
     identifier: OUT std_logic_vector(5 downto 0);
-    octetRecu: OUT std_logic_vector(7 downto 0);
+    octetRecu: OUT std_logic_vector(7 downto 0)
   );
 
-END receptionTrame;
+END receptionTrame_op;
 
-ARCHITECTURE arch OF receptionTrame IS
+ARCHITECTURE arch OF receptionTrame_op IS
+SIGNAL LinSynchro_int : std_logic;
 
+COMPONENT D_FF
+  PORT(
+    H: IN std_logic;
+    D: IN std_logic;
+    nRst: IN std_logic;
+    Q: OUT std_logic
+  );
+END COMPONENT;
+
+COMPONENT shift_register
+  GENERIC (
+    WIDTH: integer
+  );
+  PORT(
+    H: IN std_logic;
+    H_EN: IN std_logic;
+    nRst : IN std_logic;
+    D: IN std_logic;
+    Q: OUT std_logic_vector
+  );
+END COMPONENT;
 BEGIN
 
+LinSynchro <= LinSynchro_int;
+
 -- Lin sync D-FF, with asynchronous reset
-LinSync : PROCESS(nCLR, H)
+Lin_in_sync : D_FF
-BEGIN
+  PORT MAP(
-  IF(nCLR = '0') THEN
+    H => H,
-    LinSynchro <= '0';
+    D => Lin,
-  ELSIF(rising_edge(H)) THEN
+    nRst => nCLR,
-    LinSynchro <= Lin;
+    Q => LinSynchro_int
-  END IF;
+  );
-END PROCESS LinSync;
-
 
+-- Lin serial->parallel shift reg
+Lin_para : shift_register
+  GENERIC MAP(
+    WIDTH => 8
+  )
+  PORT MAP(
+    H => H,
+    H_EN => octetRecu_EN,
+    nRst => nCLR,
+    D => LinSynchro_int,
+    Q => octetRecu
+  );
 
 END ARCHITECTURE arch;

ReceptionTrame_lib/receptionTrame_tb.vhd

@@ -0,0 +1,77 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY receptionTrame_tb IS
+  GENERIC(
+    CLOCK_PERIOD : time := 10 ns
+  );
+end receptionTrame_tb;
+
+ARCHITECTURE arch OF receptionTrame_tb IS
+SIGNAL H : std_logic;
+
+COMPONENT receptionTrame_op
+  GENERIC (
+    N: integer
+  );
+  PORT (
+    H: IN std_logic;
+    nCLR: IN std_logic;
+    Lin: IN std_logic;
+
+    octetRecu_EN : IN std_logic;
+    
+    n_SELECT: IN std_logic;
+    n_LOAD: IN std_logic;
+    n_EN: IN std_logic;
+
+    nbBit_SELECT: IN std_logic;
+    nbBit_LOAD: IN std_logic;
+    nbBit_EN: IN std_logic;
+
+    identifier_EN: IN std_logic;
+
+    nbData_LOAD: IN std_logic;
+    nbData_EN: IN std_logic;
+
+    LinSynchro: OUT std_logic;
+    
+    n_0: OUT std_logic;
+    nbBit_0: OUT std_logic;
+    nbData_0: OUT std_logic;
+
+    identifier: OUT std_logic_vector(5 downto 0);
+    octetRecu: OUT std_logic_vector(7 downto 0)
+  );
+  END COMPONENT;
+BEGIN
+
+CLK_gen : PROCESS
+BEGIN
+  H <= '0';
+  WAIT FOR CLOCK_PERIOD/2;
+  H <= '1';
+  WAIT FOR CLOCK_PERIOD/2;
+END PROCESS CLK_gen;
+
+U0 : receptionTrame_op
+  GENERIC MAP(
+    N => 1200
+  )
+  PORT MAP(
+    H => H,
+    nCLR => '1',
+    Lin => '1',
+    octetRecu_EN => '1',
+    n_SELECT => '0',
+    n_LOAD => '0',
+    n_EN => '0',
+    nbBit_SELECT => '0',
+    nbBit_LOAD => '0',
+    nbBit_EN => '0',
+    identifier_EN => '0',
+    nbData_LOAD => '0',
+    nbData_EN => '0'
+  );
+END ARCHITECTURE arch;

fusesoc.conf

@@ -16,3 +16,9 @@ sync-uri = STDLIB_lib
 sync-type = local
 auto-sync = true
 
+[library.ReceptionTrame]
+location = /home/leo/Sketchbook/VHDL/LIN_receiver/RecepteurLIN_lib/ReceptionTrame_lib
+sync-uri = ReceptionTrame_lib
+sync-type = local
+auto-sync = true
+