sensible names for components
This commit is contained in:
parent
20efb50dec
commit
9198c9dd9b
@ -244,7 +244,7 @@ BEGIN
|
||||
END PROCESS u_5seq_proc;
|
||||
|
||||
-- Instance port mappings.
|
||||
U_2 : FrameReception
|
||||
FrameRec : FrameReception
|
||||
PORT MAP (
|
||||
H => H,
|
||||
Lin => LIN,
|
||||
@ -257,7 +257,7 @@ BEGIN
|
||||
RecByte_RST => RecByte_RST,
|
||||
RecByte_WR => RecByte_WR
|
||||
);
|
||||
U_0 : InterfaceMicroprocesseur
|
||||
IntuP : InterfaceMicroprocesseur
|
||||
PORT MAP (
|
||||
CnD => CnD,
|
||||
EtatLu => EtatLu,
|
||||
@ -273,7 +273,7 @@ BEGIN
|
||||
SelAdr => SelAdr,
|
||||
D07 => D07
|
||||
);
|
||||
U_3 : InternalState
|
||||
IntState : InternalState
|
||||
PORT MAP (
|
||||
Errors_SET => Errors_SET,
|
||||
EtatLu_RST => EtatLu_RST,
|
||||
|
Loading…
x
Reference in New Issue
Block a user