leo/linreceiver-vhdl
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sensible names for components

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leo 2023-11-16 22:32:06 +01:00
parent 20efb50dec
commit 9198c9dd9b
Signed by: leo
GPG Key ID: 0DD993BFB2B307DB
1 changed files with 3 additions and 3 deletions
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recepteurlin_struct.vhd
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@ -244,7 +244,7 @@ BEGIN
END PROCESS u_5seq_proc; END PROCESS u_5seq_proc;
-- Instance port mappings. -- Instance port mappings.
U_2 : FrameReception FrameRec : FrameReception
PORT MAP ( PORT MAP (
H => H, H => H,
Lin => LIN, Lin => LIN,
@ -257,7 +257,7 @@ BEGIN
RecByte_RST => RecByte_RST, RecByte_RST => RecByte_RST,
RecByte_WR => RecByte_WR RecByte_WR => RecByte_WR
); );
U_0 : InterfaceMicroprocesseur IntuP : InterfaceMicroprocesseur
PORT MAP ( PORT MAP (
CnD => CnD, CnD => CnD,
EtatLu => EtatLu, EtatLu => EtatLu,
@ -273,7 +273,7 @@ BEGIN
SelAdr => SelAdr, SelAdr => SelAdr,
D07 => D07 D07 => D07
); );
U_3 : InternalState IntState : InternalState
PORT MAP ( PORT MAP (
Errors_SET => Errors_SET, Errors_SET => Errors_SET,
EtatLu_RST => EtatLu_RST, EtatLu_RST => EtatLu_RST,