sync break

ReceptionTrame_lib/ReceptionTrame.core

@@ -6,6 +6,8 @@ filesets:
   rtl:
     files:
       - receptionTrame_op.vhd
+      - receptionTrame.vhd
+      - receptionTrame_com.vhd
     file_type: vhdlSource
     depend:
       - ETN4:STDLIB:STDLIB:1.0.0
@@ -35,7 +37,7 @@ targets:
         analyze_options:
           - -fsynopsys
         run_options:
-          - --wave=waveform.ghw --stop-time=2us
+          - --wave=waveform.ghw
     parameters:
 
   synth:

ReceptionTrame_lib/receptionTrame.vhd

@@ -0,0 +1,51 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY receptionTrame IS
+  PORT(
+    H: IN std_logic;
+    nCLR: IN std_logic;
+    Lin: IN std_logic
+  );
+END receptionTrame;
+
+ARCHITECTURE arch OF receptionTrame IS
+  COMPONENT receptionTrame_op
+    GENERIC(
+      N: integer := 1200;
+      N_WIDTH : integer := 11
+    );
+    PORT(
+      H: IN std_logic;
+      nCLR: IN std_logic;
+      Lin: IN std_logic;
+
+      octetRecu_EN : IN std_logic;
+    
+      n_SELECT: IN std_logic;
+      n_LOAD: IN std_logic;
+      n_EN: IN std_logic;
+
+      nbBit_SELECT: IN std_logic;
+      nbBit_LOAD: IN std_logic;
+      nbBit_EN: IN std_logic;
+
+      identifier_EN: IN std_logic;
+
+      nbData_LOAD: IN std_logic;
+      nbData_EN: IN std_logic;
+
+      LinSynchro: OUT std_logic;
+    
+      n_0: OUT std_logic;
+      nbBit_0: OUT std_logic;
+      nbData_0: OUT std_logic;
+
+      identifier: OUT std_logic_vector(5 downto 0);
+      octetRecu: OUT std_logic_vector(7 downto 0)
+    );
+  END COMPONENT;
+BEGIN
+
+END ARCHITECTURE arch;

ReceptionTrame_lib/receptionTrame_com.vhd

@@ -0,0 +1,138 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY receptionTrame_com IS
+  PORT(
+    H: IN std_logic;
+    nRST: IN std_logic;
+    LinSynchro: IN std_logic;
+    
+    n_SELECT: OUT std_logic;
+    n_LOAD: OUT std_logic;
+    n_EN: OUT std_logic;
+
+    nbBit_SELECT: OUT std_logic;
+    nbBit_LOAD: OUT std_logic;
+    nbBit_EN: OUT std_logic;
+
+    identifier_EN: OUT std_logic;
+
+    nbData_LOAD: OUT std_logic;
+    nbData_EN: OUT std_logic;
+    
+    n_0: IN std_logic;
+    nbBit_0: IN std_logic;
+    nbData_0: IN std_logic
+  );
+END receptionTrame_com;
+
+ARCHITECTURE arch of receptionTrame_com IS
+TYPE state IS (waiting, syncBreak0, syncBreak1, syncFieldWait, syncFieldStart, syncFieldData, syncFieldStop, idFieldWait);
+SIGNAL cState, nState : state;
+BEGIN
+
+stateUpd : PROCESS(H, nRST)
+BEGIN
+  IF(nRST = '0') THEN
+    cState <= waiting;
+  ELSIF(rising_edge(H)) THEN
+    cState <= nState;
+  END IF;
+END process stateUpd;
+
+nStateUpd : PROCESS(LinSynchro, cState, n_0, nbBit_0)
+BEGIN
+nState <= cState;
+CASE cState IS
+  WHEN waiting =>
+    if(LinSynchro = '0') THEN
+      nState <= syncBreak0;
+    END IF;
+    
+  WHEN syncBreak0 =>
+    if(LinSynchro = '1') THEN
+      if(nbBit_0 = '1') THEN
+        nState <= syncBreak1;
+      else
+        nState <= waiting;
+      END IF;
+    END IF;
+    
+  WHEN syncBreak1 =>
+    if(LinSynchro = '0') THEN
+      if(n_0 = '1') THEN
+        nState <= syncFieldWait;
+      else
+        nState <= waiting;
+      end if;
+    END IF;
+
+  WHEN syncFieldWAit =>
+    if(LinSynchro = '0') THEN
+      nState <= syncFieldStart;
+    END IF;
+
+  WHEN syncFieldStart =>
+    if(n_0 = '1') THEN
+      IF(LinSynchro = '0') THEN
+        nState <= syncFieldData;
+      else
+        nState <= waiting;
+      END IF;
+    end if;
+
+  WHEN syncFieldData =>
+    if(nbBit_0 = '1') THEN
+      nState <= syncFieldStop;
+    END IF;
+
+  WHEN syncFieldStop =>
+    if(n_0 = '1') THEN
+      if(LinSynchro = '1') THEN
+        nState <= idFieldWait;
+      else
+        nState <= waiting;
+      end if;
+    end if;
+
+  WHEN others =>
+  end CASE;
+END PROCESS nStateUpd;
+
+RCS : PROCESS(cState, LinSynchro, n_0)
+BEGIN
+  CASE cState IS
+    WHEN waiting =>
+      if(LinSynchro = '0') THEN
+        n_LOAD <= '1';
+        n_SELECT <= '1';
+        nbBit_LOAD <= '1';
+        nbBit_SELECT <= '0';
+      end IF;
+    WHEN syncBreak0 =>
+      if(LinSynchro = '1') then
+        if(nbBit_0 = '1') then
+          n_LOAD <= '1';
+          n_SELECT <= '0';
+        else
+          -- ERROR sync
+        end if;
+      else
+        if(n_0 = '1') then
+          n_select <= '0';
+          n_LOAD <= '1';
+          nbBit_EN <= '1';
+        else
+          n_LOAD <= '0';
+          nbBit_EN <= '0';
+        end if;
+        n_EN <= '1';
+        nbBit_LOAD <= '0';
+      end if;
+    WHEN others =>
+      
+  end CASE;
+END PROCESS RCS;
+
+END ARCHITECTURE arch;

ReceptionTrame_lib/receptionTrame_op_tb.vhd

@@ -0,0 +1,77 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY receptionTrame_op_tb IS
+  GENERIC(
+    CLOCK_PERIOD : time := 10 ns
+  );
+end receptionTrame_op_tb;
+
+ARCHITECTURE arch OF receptionTrame_op_tb IS
+SIGNAL H : std_logic;
+
+COMPONENT receptionTrame_op
+  GENERIC (
+    N: integer
+  );
+  PORT (
+    H: IN std_logic;
+    nCLR: IN std_logic;
+    Lin: IN std_logic;
+
+    octetRecu_EN : IN std_logic;
+    
+    n_SELECT: IN std_logic;
+    n_LOAD: IN std_logic;
+    n_EN: IN std_logic;
+
+    nbBit_SELECT: IN std_logic;
+    nbBit_LOAD: IN std_logic;
+    nbBit_EN: IN std_logic;
+
+    identifier_EN: IN std_logic;
+
+    nbData_LOAD: IN std_logic;
+    nbData_EN: IN std_logic;
+
+    LinSynchro: OUT std_logic;
+    
+    n_0: OUT std_logic;
+    nbBit_0: OUT std_logic;
+    nbData_0: OUT std_logic;
+
+    identifier: OUT std_logic_vector(5 downto 0);
+    octetRecu: OUT std_logic_vector(7 downto 0)
+  );
+  END COMPONENT;
+BEGIN
+
+CLK_gen : PROCESS
+BEGIN
+  H <= '0';
+  WAIT FOR CLOCK_PERIOD/2;
+  H <= '1';
+  WAIT FOR CLOCK_PERIOD/2;
+END PROCESS CLK_gen;
+
+U0 : receptionTrame_op
+  GENERIC MAP(
+    N => 1200
+  )
+  PORT MAP(
+    H => H,
+    nCLR => '1',
+    Lin => '1',
+    octetRecu_EN => '1',
+    n_SELECT => '0',
+    n_LOAD => '1',
+    n_EN => '1',
+    nbBit_SELECT => '0',
+    nbBit_LOAD => '1',
+    nbBit_EN => '1',
+    identifier_EN => '0',
+    nbData_LOAD => '1',
+    nbData_EN => '1'
+  );
+END ARCHITECTURE arch;

ReceptionTrame_lib/receptionTrame_tb.vhd

@@ -4,18 +4,41 @@ USE ieee.std_logic_arith.all;
 
 ENTITY receptionTrame_tb IS
   GENERIC(
-    CLOCK_PERIOD : time := 10 ns
+    CLOCK_PERIOD: time := 52 us;
+    UC_CLK_PERIOD: time := 10 ns
   );
-end receptionTrame_tb;
+END receptionTrame_tb;
 
-ARCHITECTURE arch OF receptionTrame_tb IS
-SIGNAL H : std_logic;
+ARCHITECTURE arch of receptionTrame_tb IS
+SIGNAL Lin: std_logic;
+SIGNAL H: std_logic;
+
+SIGNAL octetRecu_EN : std_logic;
+SIGNAL n_SELECT: std_logic;
+SIGNAL n_LOAD: std_logic;
+SIGNAL n_EN: std_logic;
+
+SIGNAL nbBit_SELECT: std_logic;
+SIGNAL nbBit_LOAD: std_logic;
+SIGNAL nbBit_EN: std_logic;
+
+SIGNAL identifier_EN: std_logic;
+
+SIGNAL nbData_LOAD: std_logic;
+SIGNAL nbData_EN: std_logic;
+
+SIGNAL LinSynchro: std_logic;
+    
+SIGNAL n_0: std_logic;
+SIGNAL nbBit_0: std_logic;
+SIGNAL nbData_0: std_logic;
 
 COMPONENT receptionTrame_op
-  GENERIC (
-    N: integer
+  GENERIC(
+    N: integer := 1200;
+    N_WIDTH : integer := 11
   );
-  PORT (
+  PORT(
     H: IN std_logic;
     nCLR: IN std_logic;
     Lin: IN std_logic;
@@ -44,34 +67,137 @@ COMPONENT receptionTrame_op
     identifier: OUT std_logic_vector(5 downto 0);
     octetRecu: OUT std_logic_vector(7 downto 0)
   );
-  END COMPONENT;
-BEGIN
+END COMPONENT;
 
-CLK_gen : PROCESS
+COMPONENT receptionTrame_com
+  PORT(
+    H: IN std_logic;
+    nRST: IN std_logic;
+    LinSynchro: IN std_logic;
+    
+    n_SELECT: OUT std_logic;
+    n_LOAD: OUT std_logic;
+    n_EN: OUT std_logic;
+
+    nbBit_SELECT: OUT std_logic;
+    nbBit_LOAD: OUT std_logic;
+    nbBit_EN: OUT std_logic;
+
+    identifier_EN: OUT std_logic;
+
+    nbData_LOAD: OUT std_logic;
+    nbData_EN: OUT std_logic;
+    
+    n_0: IN std_logic;
+    nbBit_0: IN std_logic;
+    nbData_0: IN std_logic
+  );
+END COMPONENT receptionTrame_com;
 BEGIN
-  H <= '0';
-  WAIT FOR CLOCK_PERIOD/2;
-  H <= '1';
-  WAIT FOR CLOCK_PERIOD/2;
-END PROCESS CLK_gen;
 
 U0 : receptionTrame_op
   GENERIC MAP(
-    N => 1200
+    N => 1200,
+    N_WIDTH => 11
   )
   PORT MAP(
     H => H,
     nCLR => '1',
-    Lin => '1',
-    octetRecu_EN => '1',
-    n_SELECT => '0',
-    n_LOAD => '1',
-    n_EN => '1',
-    nbBit_SELECT => '0',
-    nbBit_LOAD => '1',
-    nbBit_EN => '1',
-    identifier_EN => '0',
-    nbData_LOAD => '1',
-    nbData_EN => '1'
+    Lin => Lin,
+
+    octetRecu_EN => octetRecu_EN,
+    n_SELECT => n_SELECT,
+    n_LOAD => n_LOAD,
+    n_EN => n_EN,
+    nbBit_SELECT => nbBit_SELECT,
+    nbBit_LOAD => nbBit_LOAD,
+    nbBit_EN => nbBit_EN,
+    identifier_EN => identifier_EN,
+    nbData_LOAD => nbData_LOAD,
+    nbData_EN => nbData_EN,
+    LinSynchro => LinSynchro,
+    n_0 => n_0,
+    nbBit_0 => nbBit_0,
+    nbData_0 => nbData_0
   );
-END ARCHITECTURE arch;
+
+U1 : receptionTrame_com
+  PORT MAP(
+    H => H,
+    nRST => '1',
+    LinSynchro => LinSynchro,
+    
+    n_SELECT => n_SELECT,
+    n_LOAD => n_LOAD,
+    n_EN => n_EN,
+
+    nbBit_SELECT => nbBit_SELECT,
+    nbBit_LOAD => nbBit_LOAD,
+    nbBit_EN => nbBit_EN,
+
+    identifier_EN => identifier_EN,
+
+    nbData_LOAD => nbData_LOAD,
+    nbData_EN => nbData_EN,
+    
+    n_0 => n_0,
+    nbBit_0 => nbBit_0,
+    nbData_0 => nbData_0
+  );
+
+clkGen : PROCESS
+BEGIN
+  H <= '1';
+  WAIT FOR UC_CLK_PERIOD / 2;
+  H <= '0';
+  WAIT FOR UC_CLK_PERIOD / 2;
+END PROCESS clkGen;
+
+linFrame : PROCESS
+BEGIN
+  Lin <= '1';
+  WAIT FOR 100 us;
+  -- Sync Break
+  Lin <= '0';
+  WAIT FOR 14 * CLOCK_PERIOD;
+  Lin <= '1';
+  WAIT FOR 2 * CLOCK_PERIOD;
+
+  -- Sync field
+  for i in 4 downto 0 loop
+    Lin <= '0';
+    WAIT FOR CLOCK_PERIOD;
+    Lin <= '1';
+    WAIT FOR CLOCK_PERIOD;
+  end loop;
+
+  -- ID field (0x0, 2 data byte)
+  Lin <= '0';
+  WAIT FOR CLOCK_PERIOD;
+  Lin <= '0';
+  WAIT FOR 8 * CLOCK_PERIOD;
+  Lin <= '1';
+  WAIT FOR CLOCK_PERIOD;
+
+  -- data fields (both 0x00)
+  Lin <= '0';
+  WAIT FOR 8 * CLOCK_PERIOD;
+  Lin <= '1';
+  WAIT FOR CLOCK_PERIOD;
+
+  Lin <= '0';
+  WAIT FOR 8 * CLOCK_PERIOD;
+  Lin <= '1';
+  WAIT FOR CLOCK_PERIOD;
+
+  -- checksum (0x0)
+  Lin <= '0';
+  WAIT FOR 8 * CLOCK_PERIOD;
+  Lin <= '1';
+  WAIT FOR CLOCK_PERIOD;
+
+  report "Finished"  severity failure ;
+
+END PROCESS;
+
+END ARCHITECTURE arch;

STDLIB_lib/counter.vhd

@@ -31,14 +31,16 @@ main : PROCESS(H, nRst)
 BEGIN
   if(nRst = '0') then
     cmp <= to_unsigned(0, WIDTH);
-  elsif(rising_edge(H) and H_EN = '1') then
+  elsif(rising_edge(H)) then
     if(LOAD = '1') then
       cmp <= INIT;
-    elsif(cmp /= MAX_VAL) then
-      if(upnDown = '1') then
-        cmp <= cmp + 1;
-      else
-        cmp <= cmp - 1;
+    elsif(H_EN = '1') then
+      if(cmp /= MAX_VAL) then
+        if(upnDown = '1') then
+          cmp <= cmp + 1;
+        else
+          cmp <= cmp - 1;
+        end if;
       end if;
     end if;
   end if;