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Update from HDLDesigner srcs, (HDLDesigner will be the bane of my existence)

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This commit is contained in:
leo 2023-11-01 17:23:29 +01:00
parent c5c757f1ff
commit e49ee0caee
Signed by: leo
GPG Key ID: 0DD993BFB2B307DB
15 changed files with 1885 additions and 563 deletions
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190
InterfaceMicroprocesseur_lib/InterfaceMicroprocesseur_SousTest.vhd
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@ -1,96 +1,136 @@
-- VHDL generated by me
-- VHDL Entity RecepteurLIN_lib.InterfaceMicroprocesseur_SousTest.symbol
--
-- Created:
-- by - e208835u.UNKNOWN (irb121-03)
-- at - 10:37:09 12/09/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY InterfaceMicroprocesseur_SousTest IS
-- Declarations
END InterfaceMicroprocesseur_SousTest;
END InterfaceMicroprocesseur_SousTest ;
--
-- VHDL Architecture RecepteurLIN_lib.InterfaceMicroprocesseur_SousTest.struct
--
-- Created:
-- by - e208835u.UNKNOWN (irb121-03)
-- at - 10:59:28 12/09/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
-- LIBRARY RecepteurLIN_lib;
ARCHITECTURE struct OF InterfaceMicroprocesseur_SousTest IS
SIGNAL D07 : std_logic_vector(7 DOWNTO 0);
SIGNAL dout : std_logic_vector(7 DOWNTO 0);
SIGNAL dout1 : std_logic_vector(7 DOWNTO 0);
SIGNAL H : std_logic;
-- Architecture declarations
-- Internal signal declarations
SIGNAL CnD : std_logic;
SIGNAL D07 : std_logic_vector(7 DOWNTO 0);
SIGNAL H : std_logic;
SIGNAL M_Received : std_logic;
SIGNAL RnW : std_logic;
SIGNAL dout : std_logic_vector(7 DOWNTO 0);
SIGNAL dout1 : std_logic_vector(7 DOWNTO 0);
SIGNAL nCS : std_logic;
SIGNAL nRST : std_logic;
-- Component Declarations
COMPONENT EnvTest_InterfaceMicroprocesseur
GENERIC (
CLOCK_PERIOD : time := 50 ns;
RESET_OFFSET : time := 500 ns;
RESET_DURATION : time := 300 ns;
ACCESS_TIME : time := 40 ns;
HOLD_TIME : time := 70 ns
);
PORT (
D07 : INOUT std_logic_vector (7 DOWNTO 0);
nRST : OUT std_logic;
H : OUT std_logic;
M_Received : IN std_logic;
CnD : OUT std_logic;
RnW : OUT std_logic;
nCS : OUT std_logic
);
GENERIC (
CLOCK_PERIOD : time := 50 ns;
RESET_OFFSET : time := 500 ns;
RESET_DURATION : time := 300 ns;
ACCESS_TIME : time := 40 ns;
HOLD_TIME : time := 70 ns
);
PORT (
M_Received : IN std_logic ;
CnD : OUT std_logic ;
H : OUT std_logic ;
RnW : OUT std_logic ;
nCS : OUT std_logic ;
nRST : OUT std_logic ;
D07 : INOUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT InterfaceMicroprocesseur
PORT (
SelAdr : OUT std_logic_vector (7 DOWNTO 0);
D07 : INOUT std_logic_vector (7 DOWNTO 0);
EtatLu : IN std_logic_vector (7 DOWNTO 0);
OctetLu : IN std_logic_vector (7 DOWNTO 0);
H : IN std_logic;
nRST : IN std_logic;
CnD : IN std_logic;
RnW : IN std_logic;
nCS : IN std_logic;
DecNbOctet : OUT std_logic;
EtatLu_RST : OUT std_logic;
M_Received : OUT std_logic;
OctetLu_RD : OUT std_logic
);
PORT (
CnD : IN std_logic ;
EtatLu : IN std_logic_vector (7 DOWNTO 0);
H : IN std_logic ;
OctetLu : IN std_logic_vector (7 DOWNTO 0);
RnW : IN std_logic ;
nCS : IN std_logic ;
nRST : IN std_logic ;
DecNbOctet : OUT std_logic ;
EtatLu_RST : OUT std_logic ;
M_Received : OUT std_logic ;
OctetLu_RD : OUT std_logic ;
SelAdr : OUT std_logic_vector (7 DOWNTO 0);
D07 : INOUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
dout <= "00001000";
dout1 <= "00001010";
U_0 : EnvTest_InterfaceMicroprocesseur
GENERIC MAP (
CLOCK_PERIOD => 50 ns,
RESET_OFFSET => 500 ns,
RESET_DURATION => 300 ns,
ACCESS_TIME => 40 ns,
HOLD_TIME => 70 ns
)
PORT MAP (
M_Received => M_Received,
CnD => CnD,
H => H,
RnW => RnW,
nCS => nCS,
nRST => nRST,
D07 => D07
);
U_1 : InterfaceMicroprocesseur
PORT MAP (
CnD => CnD,
EtatLu => dout1,
H => H,
OctetLu => dout,
RnW => RnW,
nCS => nCS,
nRST => nRST,
DecNbOctet => OPEN,
EtatLu_RST => OPEN,
M_Received => M_Received,
OctetLu_RD => OPEN,
SelAdr => OPEN,
D07 => D07
);
-- Optional embedded configurations
-- pragma synthesis_off
-- FOR ALL : EnvTest_InterfaceMicroprocesseur USE ENTITY RecepteurLIN_lib.EnvTest_InterfaceMicroprocesseur;
-- FOR ALL : InterfaceMicroprocesseur USE ENTITY RecepteurLIN_lib.InterfaceMicroprocesseur;
-- pragma synthesis_on
BEGIN
-- ModuleWare code(v1.12) for instance 'U_2' of 'constval'
dout <= "00001000";
-- ModuleWare code(v1.12) for instance 'U_3' of 'constval'
dout1 <= "00001010";
-- Instance port mappings.
U_0 : EnvTest_InterfaceMicroprocesseur
GENERIC MAP (
CLOCK_PERIOD => 50 ns,
RESET_OFFSET => 500 ns,
RESET_DURATION => 300 ns,
ACCESS_TIME => 40 ns,
HOLD_TIME => 70 ns
)
PORT MAP (
M_Received => M_Received,
CnD => CnD,
H => H,
RnW => RnW,
nCS => nCS,
nRST => nRST,
D07 => D07
);
U_1 : InterfaceMicroprocesseur
PORT MAP (
CnD => CnD,
EtatLu => dout1,
H => H,
OctetLu => dout,
RnW => RnW,
nCS => nCS,
nRST => nRST,
DecNbOctet => OPEN,
EtatLu_RST => OPEN,
M_Received => M_Received,
OctetLu_RD => OPEN,
SelAdr => OPEN,
D07 => D07
);
END struct;

17
LIN_Rec_Test_Env_2022_IP/LIN_Rec_Test_Env_2022_IP.core Normal file
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@ -0,0 +1,17 @@
CAPI=2:
name: ETN4:conceptionCircuits:LIN_TB:1.0.0
description: Testbench IP for the LIN receiver
filesets:
rtl:
files:
- lin_receiver_env_flow_2016.vhd
- testeur_struct.vhd
file_type: vhdlSource
targets:
default: &default
filesets:
- rtl
toplevel:
parameters:

320
LIN_Rec_Test_Env_2022_IP/lin_receiver_env_flow_2016.vhd Normal file
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@ -0,0 +1,320 @@
-- VHDL Entity LIN_Rec_Env.LIN_Receiver_Env.symbol
--
-- Created:
-- by - UNKNOWN.UNKNOWN (IRSEII23)
-- at - 16:44:27 09/04/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY LIN_Receiver_Env IS
GENERIC(
sur_ech : integer := 1024
);
PORT(
M_Received : IN std_logic;
C_Dbar : OUT std_logic;
Cs_bar : OUT std_logic;
LIN : OUT std_logic;
Master_Clk : OUT std_logic;
R_Wbar : OUT std_logic;
Reset_bar : OUT std_logic;
Data_Bus : INOUT std_logic_vector ( 7 DOWNTO 0 )
);
-- Declarations
END LIN_Receiver_Env ;
--
-- VHDL Architecture LIN_Rec_Env.LIN_Receiver_Env.flow_2016
--
-- Created:
-- by - guyonnet-p.None (IRSEII23)
-- at - 12:09:01 07/13/16
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE flow_2016 OF LIN_Receiver_Env IS
-- Architecture declarations
-- PG 16/06/2016
-- CONSTANT Duree_Bit : time := 52000 ns; -- base: 19200 bits/s
CONSTANT Duree_Bit : time := 52080 ns; -- base: 19200 bits/s
CONSTANT T_Before_Reset : time := 55 ns;
CONSTANT T_Reset_Step : time := 100 ns;
CONSTANT Setup_Time: time := 5 ns;
CONSTANT Hold_time : time := 15 ns;
CONSTANT Rd_Access_Duration : time := 100 ns;
CONSTANT Wr_Access_Duration : time := 100 ns;
CONSTANT Error_on : boolean := True;
CONSTANT Error_off : boolean := False;
TYPE Def_Lenght IS (Double,Deux,Quatre,Huit);
TYPE Def_Byte IS ARRAY (7 DOWNTO 0) of std_logic;
TYPE Def_Mess IS ARRAY(0 TO 7) of Def_Byte;
PROCEDURE ReadState (signal Cs, C_D, R_W : out std_logic)
is
begin
Cs <= '1'; C_D <='1'; R_W <= '1';
wait for Setup_Time;
Cs <= '0'; C_D <='1'; R_W <= '1';
wait for Rd_Access_Duration;
Cs <= '1'; C_D <='1'; R_W <= '1';
wait for Hold_Time;
Cs <= '1'; C_D <='1'; R_W <= '1';
end ReadState;
PROCEDURE ReadData (signal Cs, C_D, R_W : out std_logic)
is
begin
Cs <= '1'; C_D <='0'; R_W <= '1';
wait for Setup_Time;
Cs <= '0'; C_D <='0'; R_W <= '1';
wait for Rd_Access_Duration;
Cs <= '1'; C_D <='0'; R_W <= '1';
wait for Hold_Time;
Cs <= '1'; C_D <='1'; R_W <= '1';
end ReadData;
PROCEDURE WriteMask (constant Byte_To_Write : std_logic_vector;
signal Cs, C_D, R_W : out std_logic;
signal DataBus : out std_logic_vector(7 downto 0))
is
begin
Cs <= '1'; C_D <='1'; R_W <= '0'; DataBus <= Byte_To_Write ;
wait for Setup_Time;
Cs <= '0'; C_D <='1'; R_W <= '0'; DataBus <= Byte_To_Write ;
wait for Wr_Access_Duration;
Cs <= '1'; C_D <='1'; R_W <= '0'; DataBus <= Byte_To_Write ;
wait for Hold_Time;
Cs <= '1'; C_D <='1'; R_W <= '1'; DataBus <= (others => 'Z') ;
end WriteMask;
PROCEDURE WriteAdr (constant Byte_To_Write : std_logic_vector;
signal Cs, C_D, R_W : out std_logic;
signal DataBus : out std_logic_vector(7 downto 0))
is
begin
Cs <= '1'; C_D <='0'; R_W <= '0'; DataBus <= Byte_To_Write ;
wait for Setup_Time;
Cs <= '0'; C_D <='0'; R_W <= '0'; DataBus <= Byte_To_Write ;
wait for Wr_Access_Duration;
Cs <= '1'; C_D <='0'; R_W <= '0'; DataBus <= Byte_To_Write ;
wait for Hold_Time;
Cs <= '1'; C_D <='1'; R_W <= '1'; DataBus <= (others => 'Z') ;
end WriteAdr;
PROCEDURE Send_Brk(
constant Low_Duration : natural;
constant High_Duration : natural;
signal Loc_Lout : out std_logic)
is
begin
Loc_Lout <= '0';
wait for (Low_Duration * Duree_Bit);
Loc_Lout <= '1';
wait for (High_Duration * Duree_Bit);
end Send_Brk;
PROCEDURE Send(constant Err : boolean;
constant Byte_TBS : Def_Byte;
signal Loc_Lout : out std_logic)
is
variable i : natural;
begin
-- ---------------------------------------------------------- START BIT XMIT
Loc_Lout <= '0';
wait for Duree_Bit;
-- ---------------------------------------------------------- DATA BITS XMIT LOOP
for i in 0 to 7
loop
Loc_Lout <= Byte_TBS(i);
wait for Duree_Bit;
end loop;
-- ---------------------------------------------------------- STOP BIT XMIT DEPENDING ON Err BOOLEAN
if Err
-- ---------------------------------------------------------- BAD STOP XMIT WITH EXTENDED DURATION (1,5 bit : easier to see in waveforms)
then Loc_Lout <= '0';
wait for ((3*Duree_Bit/2));
-- ---------------------------------------------------------- RESTORE IDLE STATE AFTER BAD STOP XMIT
Loc_Lout <= '1';
-- ---------------------------------------------------------- GOOD STOP XMIT WITH NORMAL DURATION
else Loc_Lout <= '1';
wait for Duree_Bit;
end if;
end Send;
PROCEDURE Send_Mess(
constant Err : boolean;
constant Length_Code : Def_Lenght;
constant Mess_Data : Def_Mess;
signal Loc_Lout : out std_logic)
is
variable Nb_Bytes : natural;
variable IdField : Def_Byte;
begin
-- ---------------------------------------------------------- BREAK HIGH + LOW XMIT
Send_Brk(15,3,Loc_Lout);
-- ---------------------------------------------------------- SYNC BYTE XMIT
Send(False, x"55",Loc_Lout);
-- ---------------------------------------------------------- INTER-BYTE SPACE
wait for (3 * Duree_Bit);
-- ---------------------------------------------------------- IDENTIFIER CODE DETERMINATION
case Length_Code is
-- PG 16/06/2016
-- when Huit => Nb_Bytes:=7; IdField:=b"00_11_1001"; -- 39h 2014 value
when Huit => Nb_Bytes:=7; IdField:=b"01_11_1001"; -- 79h 2016 value
-- PG 16/06/2016
when Quatre => Nb_Bytes:=3; IdField:=b"01_10_1101";-- 6Dh 2014 & 2016 value
-- PG 16/06/2016
-- when Deux => Nb_Bytes:=1; IdField:=b"10_01_0011"; -- 93h 2014 value
when Deux => Nb_Bytes:=1; IdField:=b"00_01_0111"; -- 17h 2016 value
-- PG 16/06/2016
-- when Double => Nb_Bytes:=1; IdField:=b"11_00_0110";-- C6h 2014 value
when Double => Nb_Bytes:=1; IdField:=b"11_01_0110";-- D6h 2016 value
end case;
-- ---------------------------------------------------------- IDENT BYTE XMIT
Send(False, IdField,Loc_Lout);
-- ---------------------------------------------------------- INTER-BYTE SPACE
wait for (3 * Duree_Bit);
-- ---------------------------------------------------------- (Nb_Bytes + 1) DATA BYTES XMIT
for i in 0 to Nb_Bytes
loop
-- ---------------------------------------------------------- MEDIAN BYTE WILL CATCH ERROR IF Err IS ON
if (i = Nb_Bytes/2)
-- ---------------------------------------------------------- SEND BYTE ACCORDING TO Err BOOLEAN
then Send(Err,Mess_Data(i),Loc_Lout);
-- ---------------------------------------------------------- SEND CORRECT BYTE
else Send(False, Mess_Data(i), Loc_Lout);
end if;
-- ---------------------------------------------------------- INTER-BYTE SPACE
wait for (1 * Duree_Bit);
end loop;
-- ---------------------------------------------------------- CHKSUM BYTE XMIT
-- PG 16/06/2016
-- Send(False,x"99",Loc_Lout); -- CheckSum Xmit 2014 value
Send(False,x"16",Loc_Lout); -- CheckSum Xmit 2016 value
end Send_Mess;
BEGIN
-----------------------------------------------------------------
lin_master_proc : PROCESS
-----------------------------------------------------------------
BEGIN
LIN <= '1' ;
wait for 37 us;
Send_Mess(Error_off, Deux,(x"2A",x"3C",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF"),LIN);
wait for 600 us;
Send_Mess(Error_off, Huit,(x"24",x"89",x"AB",x"CD",x"EF",x"01",x"23",x"45"),LIN);
wait for 900 us;
Send_Mess(Error_off, Double,(x"C3",x"DE",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF"),LIN);
wait for 850 us;
Send_Brk(12,3,LIN);
wait for 250 us;
Send_Mess(Error_on, Quatre,(x"CB",x"A9",x"87",x"65",x"FF",x"FF",x"FF",x"FF"),LIN);
wait;
END PROCESS lin_master_proc;
-----------------------------------------------------------------
clock_gen_proc : PROCESS
-----------------------------------------------------------------
BEGIN
Master_Clk <= '0' ;
wait for 3 ns;
l0: LOOP
Master_Clk <= '0' ;
WAIT FOR Duree_Bit/(Sur_ech * 2);
Master_Clk <= '1' ;
WAIT FOR Duree_Bit/(Sur_ech * 2);
END LOOP l0;
END PROCESS clock_gen_proc;
-----------------------------------------------------------------
reset_gen_proc : PROCESS
-----------------------------------------------------------------
BEGIN
Reset_bar <= '1';
wait for T_Before_Reset;
Reset_bar <= '0' ;
wait for T_Reset_Step;
Reset_bar <= '1';
wait;
END PROCESS reset_gen_proc;
-----------------------------------------------------------------
micro_system_proc : PROCESS
-----------------------------------------------------------------
BEGIN
Cs_bar <= '1' ;
C_Dbar <= '1' ;
Data_Bus <= (others => 'Z') ;
R_Wbar <= '1' ;
wait for 4200 us;
ReadState(Cs_bar, C_Dbar, R_Wbar);
wait for 200 ns;
ReadData(Cs_bar, C_Dbar, R_Wbar);
wait for 183 ns;
ReadState(Cs_bar, C_Dbar, R_Wbar);
wait for 152 ns;
l1: FOR i IN 0 TO 4 LOOP
ReadData(Cs_bar, C_Dbar, R_Wbar);
wait for 234 ns;
END LOOP l1;
wait for 45 us;
WriteAdr("11010110", Cs_bar, C_Dbar, R_Wbar, Data_Bus);
wait for 6550 us;
ReadState(Cs_bar, C_Dbar, R_Wbar);
wait for 205 ns;
ReadData(Cs_bar, C_Dbar, R_Wbar);
wait for 1800 us;
ReadState(Cs_bar, C_Dbar, R_Wbar);
wait for 133 ns;
l2: FOR i IN 0 TO 1 LOOP
ReadData(Cs_bar, C_Dbar, R_Wbar);
wait for 127 ns;
END LOOP l2;
wait for 4900 us;
ReadState(Cs_bar, C_Dbar, R_Wbar);
wait for 134 ns;
l3: FOR i IN 0 TO 5 LOOP
ReadData(Cs_bar, C_Dbar, R_Wbar);
wait for 143 ns;
END LOOP l3;
wait for 1000 us;
ReadState(Cs_bar, C_Dbar, R_Wbar);
wait for 3660 us;
ReadState(Cs_bar, C_Dbar, R_Wbar);
wait for 830 us;
ReadData(Cs_bar, C_Dbar, R_Wbar);
wait for 1000 us;
ReadState(Cs_bar, C_Dbar, R_Wbar);
wait; -- wait forever;
END PROCESS micro_system_proc;
END flow_2016;

89
LIN_Rec_Test_Env_2022_IP/testeur_struct.vhd Normal file
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@ -0,0 +1,89 @@
-- VHDL Entity Environnement_Test_lib.Testeur.symbol
--
-- Created:
-- by - lenours-s.None (LENOURS-S-PC)
-- at - 08:38:40 10/03/16
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Testeur IS
-- Declarations
END Testeur ;
--
-- VHDL Architecture Environnement_Test_lib.Testeur.struct
--
-- Created:
-- by - lenours-s.None (LENOURS-S-PC)
-- at - 08:39:56 10/03/16
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
-- LIBRARY Environnement_Test_lib;
ARCHITECTURE struct OF Testeur IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL C_Dbar : std_logic;
SIGNAL Cs_bar : std_logic;
SIGNAL Data_Bus : std_logic_vector( 7 DOWNTO 0 );
SIGNAL LIN : std_logic;
SIGNAL M_Received : std_logic;
SIGNAL Master_Clk : std_logic;
SIGNAL R_Wbar : std_logic;
SIGNAL Reset_bar : std_logic;
-- Component Declarations
COMPONENT LIN_Receiver_Env
GENERIC (
sur_ech : integer := 1024
);
PORT (
M_Received : IN std_logic;
C_Dbar : OUT std_logic;
Cs_bar : OUT std_logic;
LIN : OUT std_logic;
Master_Clk : OUT std_logic;
R_Wbar : OUT std_logic;
Reset_bar : OUT std_logic;
Data_Bus : INOUT std_logic_vector ( 7 DOWNTO 0 )
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : LIN_Receiver_Env USE ENTITY Environnement_Test_lib.LIN_Receiver_Env;
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
U_0 : LIN_Receiver_Env
GENERIC MAP (
sur_ech => 1024
)
PORT MAP (
M_Received => M_Received,
C_Dbar => C_Dbar,
Cs_bar => Cs_bar,
LIN => LIN,
Master_Clk => Master_Clk,
R_Wbar => R_Wbar,
Reset_bar => Reset_bar,
Data_Bus => Data_Bus
);
END struct;

49
RecepteurLIN.core
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@ -2,3 +2,52 @@ CAPI=2:
name: etn4:conceptionCircuit:recepteurLIN:1.0.0
description: A LIN receiver, ETN4 project
filesets:
rtl:
files:
- recepteurlin_struct.vhd
- internalstate_struct.vhd
file_type: vhdlSource
depend:
- ETN4:conceptionCircuits:LIN_TB:1.0.0
- ETN4:recepteurLIN:ReceptionTrame:1.0.0
- ETN4:recepteurLIN:InterfaceMicroprocesseur:1.0.0
tb:
files:
- recepteurlin_undertest_struct.vhd
file_type: vhdlSource
targets:
default: &default
filesets:
- rtl
toplevel: RecepteurLIN
parameters:
sim:
<<: *default
description: Simulate the design
default_tool: ghdl
filesets_append:
- tb
toplevel: RecepteurLin_UnderTest
tools:
ghdl:
analyze_options:
- -fsynopsys
run_options:
- --wave=waveform.ghw --stop-time=5ms
parameters:
synth:
<<: *default
description: Synthesize the design
default_tool: vivado
filesets_append:
tools:
vivado:
part: xc7a35tcpg236-1
pnr: none
parameters:

4
ReceptionTrame_lib/ReceptionTrame.core
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@ -10,7 +10,7 @@ filesets:
- receptionTrame_com.vhd
file_type: vhdlSource
depend:
- ETN4:STDLIB:STDLIB:1.0.0
- ETN4:conceptionCircuits:LIN_TB:1.0.0
tb:
files:
@ -31,7 +31,7 @@ targets:
default_tool: ghdl
filesets_append:
- tb
toplevel: receptionTrame_tb
toplevel: FrameReception_UnderTest
tools:
ghdl:
analyze_options:

62
ReceptionTrame_lib/decoder_tbl.vhd Normal file
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@ -0,0 +1,62 @@
-- VHDL Entity RecepteurLIN_lib.decoder.interface
--
-- Created:
-- by - e208835u.UNKNOWN (irb121-06)
-- at - 16:35:13 19/09/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY decoder IS
PORT(
RecByte : IN std_logic_vector (5 DOWNTO 4);
DataFieldNb_INIT : OUT std_logic_vector (2 DOWNTO 0)
);
-- Declarations
END decoder ;
--
-- VHDL Architecture RecepteurLIN_lib.decoder.tbl
--
-- Created:
-- by - e208835u.UNKNOWN (irb121-06)
-- at - 16:41:56 19/09/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE tbl OF decoder IS
-- Architecture declarations
BEGIN
-----------------------------------------------------------------
truth_process_proc: PROCESS(RecByte)
-----------------------------------------------------------------
BEGIN
-- Block 1
IF (RecByte(5 DOWNTO 4) = "00") THEN
DataFieldNb_INIT <= "001";
ELSIF (RecByte(5 DOWNTO 4) = "01") THEN
DataFieldNb_INIT <= "001";
ELSIF (RecByte(5 DOWNTO 4) = "10") THEN
DataFieldNb_INIT <= "011";
ELSIF (RecByte(5 DOWNTO 4) = "11") THEN
DataFieldNb_INIT <= "111";
END IF;
END PROCESS truth_process_proc;
-- Architecture concurrent statements
END tbl;

342
ReceptionTrame_lib/receptionTrame.vhd
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@ -1,161 +1,223 @@
-- VHDL Entity RecepteurLIN_lib.FrameReception.symbol
--
-- Created:
-- by - e208835u.UNKNOWN (irb013-09)
-- at - 12:46:30 17/10/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY receptionTrame IS
PORT(
H: IN std_logic;
nCLR: IN std_logic;
Lin: IN std_logic;
ENTITY FrameReception IS
PORT(
H : IN std_logic;
Lin : IN std_logic;
SelAdr : IN std_logic_vector (7 DOWNTO 0);
nRST : IN std_logic;
ErrorSet : OUT std_logic_vector (3 DOWNTO 1);
MsgRcv_SET : OUT std_logic;
NbRecByte_Inc : OUT std_logic;
RecByte : OUT std_logic_vector (7 DOWNTO 0);
RecByte_RST : OUT std_logic;
RecByte_WR : OUT std_logic
);
AdrSel: IN std_logic_vector;
-- Declarations
RecByte: OUT std_logic_vector(7 downto 0);
RecByte_WR: OUT std_logic;
RecBytes_RST: OUT std_logic;
END FrameReception ;
Err_SET: OUT std_logic_vector(2 downto 0);
NbByteInc: OUT std_logic;
MsgReceived_SET: OUT std_logic;
NbRecByte_RST: OUT std_logic
);
END receptionTrame;
--
-- VHDL Architecture RecepteurLIN_lib.FrameReception.struct
--
-- Created:
-- by - e208835u.UNKNOWN (irb013-09)
-- at - 12:46:30 17/10/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE arch OF receptionTrame IS
SIGNAL octetRecu_EN : std_logic;
SIGNAL n_SELECT: std_logic;
SIGNAL n_LOAD: std_logic;
SIGNAL n_EN: std_logic;
-- LIBRARY RecepteurLIN_lib;
SIGNAL nbBit_SELECT: std_logic;
SIGNAL nbBit_LOAD: std_logic;
SIGNAL nbBit_EN: std_logic;
ARCHITECTURE struct OF FrameReception IS
SIGNAL identifier_EN: std_logic;
-- Architecture declarations
SIGNAL nbData_LOAD: std_logic;
SIGNAL nbData_EN: std_logic;
-- Internal signal declarations
SIGNAL BitNb_EN : std_logic;
SIGNAL BitNb_SELECT : std_logic;
SIGNAL BitsNb_0 : std_logic;
SIGNAL BitsNb_LOAD : std_logic;
SIGNAL DataFieldNb : std_logic_vector(2 DOWNTO 0);
SIGNAL DataFieldNb_0 : std_logic;
SIGNAL DataFieldNb_LOAD : std_logic;
SIGNAL IdentifierField : std_logic_vector(5 DOWNTO 0);
SIGNAL LinSynchro : std_logic;
SIGNAL dout : std_logic;
SIGNAL identifier_EN : std_logic;
SIGNAL n_0 : std_logic;
SIGNAL n_EN : std_logic;
SIGNAL n_LOAD : std_logic;
SIGNAL n_SELECT : std_logic;
SIGNAL nbData_EN : std_logic;
SIGNAL octetRecu_EN : std_logic;
SIGNAL LinSynchro: std_logic;
SIGNAL n_0: std_logic;
SIGNAL nbBit_0: std_logic;
SIGNAL nbData_0: std_logic;
COMPONENT receptionTrame_op
GENERIC(
N: integer := 1200;
N_WIDTH : integer := 11
);
PORT(
H: IN std_logic;
nCLR: IN std_logic;
Lin: IN std_logic;
-- Component Declarations
COMPONENT Command_Unit
PORT (
BitNb_0 : IN std_logic;
DataNb_0 : IN std_logic;
H : IN std_logic;
LinSynchro : IN std_logic;
nRST : IN std_logic;
n_0 : IN std_logic;
BitNb_EN : OUT std_logic;
BitNb_LOAD : OUT std_logic;
BitNb_SELECT : OUT std_logic;
ErrorSet : OUT std_logic_vector (3 DOWNTO 1);
IdentifierField_EN : OUT std_logic;
MsgRcv_SET : OUT std_logic;
RecByte_RST : OUT std_logic := '0';
RecByte_WR : OUT std_logic;
n_EN : OUT std_logic;
n_LOAD : OUT std_logic;
n_SELECT : OUT std_logic;
nbData_EN : OUT std_logic;
nbData_LOAD : OUT std_logic;
octetRecu_EN : OUT std_logic
);
END COMPONENT;
COMPONENT FrameReceptionOP
GENERIC (
N : std_logic_vector := "10000000000"
);
PORT (
BitsNb_EN : IN std_logic ;
BitsNb_LOAD : IN std_logic ;
BitsNb_SELECT : IN std_logic ;
DataFieldNb_EN : IN std_logic ;
DataFieldNb_LOAD : IN std_logic ;
H : IN std_logic ;
IdentifierField_EN : IN std_logic ;
Lin : IN std_logic ;
RecByte_EN : IN std_logic ;
nCLR : IN std_logic ;
n_EN : IN std_logic ;
n_LOAD : IN std_logic ;
n_SELECT : IN std_logic ;
BitsNb_0 : OUT std_logic ;
DataFieldNb : OUT std_logic_vector (2 DOWNTO 0);
DataFieldNb_0 : OUT std_logic ;
IdentifierField : OUT std_logic_vector (5 DOWNTO 0);
LinSynchro : OUT std_logic ;
RecByte : OUT std_logic_vector (7 DOWNTO 0);
n_0 : OUT std_logic
);
END COMPONENT;
octetRecu_EN : IN std_logic;
n_SELECT: IN std_logic;
n_LOAD: IN std_logic;
n_EN: IN std_logic;
-- Optional embedded configurations
-- pragma synthesis_off
-- FOR ALL : Command_Unit USE ENTITY RecepteurLIN_lib.Command_Unit;
-- FOR ALL : FrameReceptionOP USE ENTITY RecepteurLIN_lib.FrameReceptionOP;
-- pragma synthesis_on
nbBit_SELECT: IN std_logic;
nbBit_LOAD: IN std_logic;
nbBit_EN: IN std_logic;
identifier_EN: IN std_logic;
nbData_LOAD: IN std_logic;
nbData_EN: IN std_logic;
LinSynchro: OUT std_logic;
n_0: OUT std_logic;
nbBit_0: OUT std_logic;
nbData_0: OUT std_logic;
identifier: OUT std_logic_vector(5 downto 0);
octetRecu: OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT receptionTrame_com
PORT(
H: IN std_logic;
nRST: IN std_logic;
LinSynchro: IN std_logic;
octetRecu_EN: OUT std_logic;
n_SELECT: OUT std_logic;
n_LOAD: OUT std_logic;
n_EN: OUT std_logic;
nbBit_SELECT: OUT std_logic;
nbBit_LOAD: OUT std_logic;
nbBit_EN: OUT std_logic;
identifier_EN: OUT std_logic;
nbData_LOAD: OUT std_logic;
nbData_EN: OUT std_logic;
n_0: IN std_logic;
nbBit_0: IN std_logic;
nbData_0: IN std_logic
);
END COMPONENT receptionTrame_com;
BEGIN
U0 : receptionTrame_op
GENERIC MAP(
N => 1200,
N_WIDTH => 11
)
PORT MAP(
H => H,
nCLR => '1',
Lin => Lin,
-- ModuleWare code(v1.12) for instance 'U_2' of 'pbuf'
u_2seq_proc: PROCESS (octetRecu_EN)
BEGIN
IF (octetRecu_EN ='1' ) THEN
NbRecByte_Inc <= '1';
ELSIF (octetRecu_EN ='H' ) THEN
NbRecByte_Inc <= '1';
ELSIF (octetRecu_EN ='0' ) THEN
NbRecByte_Inc <= '0';
ELSIF (octetRecu_EN ='L' ) THEN
NbRecByte_Inc <= '0';
ELSIF (octetRecu_EN ='U' ) THEN
NbRecByte_Inc <= 'U';
ELSIF (octetRecu_EN ='X' ) THEN
NbRecByte_Inc <= 'X';
ELSIF (octetRecu_EN ='Z' ) THEN
NbRecByte_Inc <= 'X';
END IF;
END PROCESS u_2seq_proc;
octetRecu_EN => octetRecu_EN,
n_SELECT => n_SELECT,
n_LOAD => n_LOAD,
n_EN => n_EN,
nbBit_SELECT => nbBit_SELECT,
nbBit_LOAD => nbBit_LOAD,
nbBit_EN => nbBit_EN,
identifier_EN => identifier_EN,
nbData_LOAD => nbData_LOAD,
nbData_EN => nbData_EN,
LinSynchro => LinSynchro,
n_0 => n_0,
nbBit_0 => nbBit_0,
nbData_0 => nbData_0
);
-- ModuleWare code(v1.12) for instance 'U_3' of 'pbuf'
u_3seq_proc: PROCESS (octetRecu_EN)
BEGIN
IF (octetRecu_EN ='1' ) THEN
dout <= '1';
ELSIF (octetRecu_EN ='H' ) THEN
dout <= '1';
ELSIF (octetRecu_EN ='0' ) THEN
dout <= '0';
ELSIF (octetRecu_EN ='L' ) THEN
dout <= '0';
ELSIF (octetRecu_EN ='U' ) THEN
dout <= 'U';
ELSIF (octetRecu_EN ='X' ) THEN
dout <= 'X';
ELSIF (octetRecu_EN ='Z' ) THEN
dout <= 'X';
END IF;
END PROCESS u_3seq_proc;
U1 : receptionTrame_com
PORT MAP(
H => H,
nRST => '1',
LinSynchro => LinSynchro,
-- Instance port mappings.
U_0 : Command_Unit
PORT MAP (
H => H,
nRST => nRST,
LinSynchro => LinSynchro,
octetRecu_EN => octetRecu_EN,
n_SELECT => n_SELECT,
n_LOAD => n_LOAD,
n_EN => n_EN,
BitNb_SELECT => BitNb_SELECT,
BitNb_LOAD => BitsNb_LOAD,
BitNb_EN => BitNb_EN,
IdentifierField_EN => identifier_EN,
nbData_LOAD => DataFieldNb_LOAD,
nbData_EN => nbData_EN,
n_0 => n_0,
BitNb_0 => BitsNb_0,
DataNb_0 => DataFieldNb_0,
RecByte_WR => RecByte_WR,
RecByte_RST => RecByte_RST,
ErrorSet => ErrorSet,
MsgRcv_SET => MsgRcv_SET
);
U_1 : FrameReceptionOP
GENERIC MAP (
N => "10000000000"
)
PORT MAP (
BitsNb_EN => BitNb_EN,
BitsNb_LOAD => BitsNb_LOAD,
BitsNb_SELECT => BitNb_SELECT,
DataFieldNb_EN => nbData_EN,
DataFieldNb_LOAD => DataFieldNb_LOAD,
H => H,
IdentifierField_EN => identifier_EN,
Lin => Lin,
RecByte_EN => dout,
nCLR => nRST,
n_EN => n_EN,
n_LOAD => n_LOAD,
n_SELECT => n_SELECT,
BitsNb_0 => BitsNb_0,
DataFieldNb => DataFieldNb,
DataFieldNb_0 => DataFieldNb_0,
IdentifierField => IdentifierField,
LinSynchro => LinSynchro,
RecByte => RecByte,
n_0 => n_0
);
octetRecu_EN => octetRecu_EN,
n_SELECT => n_SELECT,
n_LOAD => n_LOAD,
n_EN => n_EN,
nbBit_SELECT => nbBit_SELECT,
nbBit_LOAD => nbBit_LOAD,
nbBit_EN => nbBit_EN,
identifier_EN => identifier_EN,
nbData_LOAD => nbData_LOAD,
nbData_EN => nbData_EN,
n_0 => n_0,
nbBit_0 => nbBit_0,
nbData_0 => nbData_0
);
END ARCHITECTURE arch;
END struct;

120
ReceptionTrame_lib/receptionTrame_com.vhd
View File

@ -2,7 +2,7 @@ LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY receptionTrame_com IS
ENTITY Command_Unit IS
PORT(
H: IN std_logic;
nRST: IN std_logic;
@ -14,22 +14,28 @@ ENTITY receptionTrame_com IS
n_LOAD: OUT std_logic;
n_EN: OUT std_logic;
nbBit_SELECT: OUT std_logic;
nbBit_LOAD: OUT std_logic;
nbBit_EN: OUT std_logic;
BitNb_SELECT: OUT std_logic;
BitNb_LOAD: OUT std_logic;
BitNb_EN: OUT std_logic;
identifier_EN: OUT std_logic;
IdentifierField_EN: OUT std_logic;
nbData_LOAD: OUT std_logic;
nbData_EN: OUT std_logic;
n_0: IN std_logic;
nbBit_0: IN std_logic;
nbData_0: IN std_logic
BitNb_0: IN std_logic;
DataNb_0: IN std_logic;
RecByte_WR: OUT std_logic;
RecByte_RST: OUT std_logic := '0';
ErrorSet: OUT std_logic_vector(3 downto 1);
MsgRcv_SET: OUT std_logic
);
END receptionTrame_com;
END Command_Unit;
ARCHITECTURE arch of receptionTrame_com IS
ARCHITECTURE arch of Command_Unit IS
TYPE state IS (waiting, syncBreak0, syncBreak1, syncFieldWait, syncFieldStart, syncFieldData, syncFieldStop, idFieldWait, idFieldStart, idFieldData, idFieldStop, dataFieldWait, dataFieldStart, dataFieldData, dataFieldStop, checksumFieldWait, checksumFieldStart, checksumFieldData, checksumFieldStop);
SIGNAL cState, nState : state;
@ -51,7 +57,7 @@ BEGIN
END IF;
END process stateUpd;
nStateUpd : PROCESS(LinSynchro, cState, n_0, nbBit_0)
nStateUpd : PROCESS(LinSynchro, cState, n_0, BitNb_0)
BEGIN
nState <= cState;
CASE cState IS
@ -62,7 +68,7 @@ CASE cState IS
WHEN syncBreak0 =>
if(LinSynchro = '1') THEN
if(nbBit_0 = '1') THEN
if(BitNb_0 = '1') THEN
nState <= syncBreak1;
else
nState <= waiting;
@ -93,7 +99,7 @@ CASE cState IS
end if;
WHEN syncFieldData =>
if(nbBit_0 = '1') THEN
if(BitNb_0 = '1') THEN
nState <= syncFieldStop;
END IF;
@ -121,7 +127,7 @@ CASE cState IS
end if;
WHEN idFieldData =>
if(nbBit_0 = '1') then
if(BitNb_0 = '1') then
nState <= idFieldStop;
end if;
@ -149,14 +155,14 @@ CASE cState IS
end if;
WHEN dataFieldData =>
if(nbBit_0 = '1') then
if(BitNb_0 = '1') then
nState <= dataFieldStop;
end if;
WHEN dataFieldStop =>
if(n_0 = '1') then
if(LinSynchro = '1') then
if(nbData_0 = '1') then
if(DataNb_0 = '1') then
nState <= checksumFieldWait;
else
nState <= dataFieldWait;
@ -181,7 +187,7 @@ CASE cState IS
end if;
WHEN checksumFieldData =>
if(nbBit_0 = '1') then
if(BitNb_0 = '1') then
nState <= checksumFieldStop;
end if;
@ -195,34 +201,40 @@ END PROCESS nStateUpd;
RCS : PROCESS(cState, LinSynchro, n_0)
BEGIN
BitNb_EN <= '0';
nbData_EN <= '0';
RecByte_WR <= '0';
MsgRcv_SET <= '0';
CASE cState IS
WHEN waiting =>
if(LinSynchro = '0') THEN
n_LOAD <= '1';
BitNb_EN <= '1';
n_SELECT <= '1';
nbBit_LOAD <= '1';
nbBit_SELECT <= '0';
BitNb_LOAD <= '1';
BitNb_SELECT <= '0';
end IF;
WHEN syncBreak0 =>
if(LinSynchro = '1') then
if(nbBit_0 = '1') then
if(BitNb_0 = '1') then
n_LOAD <= '1';
n_SELECT <= '0';
else
errs.ErrorSync <= '1';
end if;
else
if(n_0 = '1') then
if(n_0 = '1' AND BitNb_0 = '0') then
n_select <= '0';
n_LOAD <= '1';
nbBit_EN <= '1';
BitNb_EN <= '1';
else
n_LOAD <= '0';
nbBit_EN <= '0';
BitNb_EN <= '0';
end if;
n_EN <= '1';
nbBit_LOAD <= '0';
BitNb_LOAD <= '0';
end if;
WHEN syncBreak1 =>
@ -246,8 +258,9 @@ BEGIN
if(LinSynchro = '0') then
n_SELECT <= '0';
n_LOAD <= '1';
nbBit_SELECT <= '1';
nbBit_LOAD <= '1';
BitNb_SELECT <= '1';
BitNb_LOAD <= '1';
BitNb_EN <= '1';
else
errs.ErrorStartBit <= '1';
end if;
@ -257,7 +270,7 @@ BEGIN
end if;
WHEN syncFieldData =>
if(nbBit_0 = '1') then
if(BitNb_0 = '1') then
n_SELECT <= '0';
n_LOAD <= '1';
octetRecu_EN <= '0';
@ -265,20 +278,20 @@ BEGIN
if(n_0 = '1') then
n_LOAD <= '1';
n_SELECT <= '0';
nbBit_EN <= '1';
BitNb_EN <= '1';
octetRecu_EN <= '1';
else
n_LOAD <= '0';
nbBit_EN <= '0';
BitNb_EN <= '0';
octetRecu_EN <= '0';
end if;
nbBit_LOAD <= '0';
BitNb_LOAD <= '0';
end if;
WHEN syncFieldStop =>
if(n_0 = '1') then
if(LinSynchro = '1') then
RecByte_WR <= '1';
else
errs.ErrorStopBit <= '1';
end if;
@ -297,15 +310,16 @@ BEGIN
if(n_0 = '1') then
n_SELECT <= '0';
n_LOAD <= '1';
nbBit_SELECT <= '1';
nbBit_LOAD <= '1';
BitNb_SELECT <= '1';
BitNb_LOAD <= '1';
BitNb_EN <= '1';
else
n_LOAD <= '0';
n_EN <= '1';
end if;
WHEN idFieldData =>
if(nbBit_0 = '1') then
if(BitNb_0 = '1') then
n_SELECT <= '0';
n_LOAD <= '1';
octetRecu_EN <= '0';
@ -313,14 +327,14 @@ BEGIN
if(n_0 = '1') then
n_LOAD <= '1';
n_SELECT <= '0';
nbBit_EN <= '1';
BitNb_EN <= '1';
octetRecu_EN <= '1';
else
n_LOAD <= '0';
nbBIt_EN <= '0';
BitNb_EN <= '0';
octetRecu_EN <= '0';
end if;
nbBit_LOAD <= '0';
BitNb_LOAD <= '0';
n_EN <= '1';
end if;
@ -328,6 +342,9 @@ BEGIN
if(n_0 = '1') then
if(LinSynchro = '1') then
nbData_LOAD <= '1';
nbData_EN <= '1';
IdentifierField_EN <= '1';
RecByte_WR <= '1';
else
errs.ErrorStopBit <= '1';
end if;
@ -343,21 +360,23 @@ BEGIN
else
nbData_EN <= '0';
nbData_LOAD <= '0';
IdentifierField_EN <= '0';
end if;
WHEN dataFieldStart =>
if(n_0 = '1') then
n_SELECT <= '0';
n_LOAD <= '1';
nbBit_SELECT <= '1';
nbBit_LOAD <= '1';
BitNb_SELECT <= '1';
BitNb_LOAD <= '1';
BitNb_EN <= '1';
else
n_LOAD <= '0';
n_EN <= '1';
end if;
WHEN dataFieldData =>
if(nbBit_0 = '1') then
if(BitNb_0 = '1') then
n_SELECT <= '0';
n_LOAD <= '1';
octetRecu_EN <= '0';
@ -365,14 +384,14 @@ BEGIN
if(n_0 = '1') then
n_LOAD <= '1';
n_SELECT <= '0';
nbBit_EN <= '1';
BitNb_EN <= '1';
octetRecu_EN <= '1';
else
n_LOAD <= '0';
nbBIt_EN <= '0';
BitNb_EN <= '0';
octetRecu_EN <= '0';
end if;
nbBit_LOAD <= '0';
BitNb_LOAD <= '0';
n_EN <= '1';
end if;
@ -380,6 +399,7 @@ BEGIN
if(n_0 = '1') then
if(LinSynchro = '1') then
nbData_EN <= '1';
RecByte_WR <= '1';
else
errs.ErrorStopBit <= '1';
end if;
@ -398,15 +418,16 @@ BEGIN
if(n_0 = '1') then
n_SELECT <= '0';
n_LOAD <= '1';
nbBit_SELECT <= '1';
nbBit_LOAD <= '1';
BitNb_SELECT <= '1';
BitNb_LOAD <= '1';
BitNb_EN <= '1';
else
n_LOAD <= '0';
n_EN <= '1';
end if;
WHEN checksumFieldData =>
if(nbBit_0 = '1') then
if(BitNb_0 = '1') then
n_SELECT <= '0';
n_LOAD <= '1';
octetRecu_EN <= '0';
@ -414,21 +435,22 @@ BEGIN
if(n_0 = '1') then
n_LOAD <= '1';
n_SELECT <= '0';
nbBit_EN <= '1';
BitNb_EN <= '1';
octetRecu_EN <= '1';
else
n_LOAD <= '0';
nbBIt_EN <= '0';
BitNb_EN <= '0';
octetRecu_EN <= '0';
end if;
nbBit_LOAD <= '0';
BitNb_LOAD <= '0';
n_EN <= '1';
end if;
WHEN checksumFieldStop =>
if(n_0 = '1') then
if(LinSynchro = '1') then
RecByte_WR <= '1';
MsgRcv_SET <= '1';
else
errs.ErrorStopBit <= '1';
end if;

466
ReceptionTrame_lib/receptionTrame_op.vhd
View File

@ -1,213 +1,309 @@
-- VHDL Entity RecepteurLIN_lib.FrameReceptionOP.symbol
--
-- Created:
-- by - e208835u.UNKNOWN (irb121-06)
-- at - 17:02:12 19/09/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_arith.all;
ENTITY receptionTrame_op IS
GENERIC(
N: integer := 1200;
N_WIDTH : integer := 11
);
PORT(
H: IN std_logic;
nCLR: IN std_logic;
Lin: IN std_logic;
ENTITY FrameReceptionOP IS
GENERIC(
N : std_logic_vector := "10000000000"
);
PORT(
BitsNb_EN : IN std_logic;
BitsNb_LOAD : IN std_logic;
BitsNb_SELECT : IN std_logic;
DataFieldNb_EN : IN std_logic;
DataFieldNb_LOAD : IN std_logic;
H : IN std_logic;
IdentifierField_EN : IN std_logic;
Lin : IN std_logic;
RecByte_EN : IN std_logic;
nCLR : IN std_logic;
n_EN : IN std_logic;
n_LOAD : IN std_logic;
n_SELECT : IN std_logic;
BitsNb_0 : OUT std_logic;
DataFieldNb : OUT std_logic_vector (2 DOWNTO 0);
DataFieldNb_0 : OUT std_logic;
IdentifierField : OUT std_logic_vector (5 DOWNTO 0);
LinSynchro : OUT std_logic;
RecByte : OUT std_logic_vector (7 DOWNTO 0);
n_0 : OUT std_logic
);
octetRecu_EN : IN std_logic;
n_SELECT: IN std_logic;
n_LOAD: IN std_logic;
n_EN: IN std_logic;
-- Declarations
nbBit_SELECT: IN std_logic;
nbBit_LOAD: IN std_logic;
nbBit_EN: IN std_logic;
END FrameReceptionOP ;
identifier_EN: IN std_logic;
--
-- VHDL Architecture RecepteurLIN_lib.FrameReceptionOP.struct
--
-- Created:
-- by - e208835u.UNKNOWN (irb121-02)
-- at - 12:28:45 03/10/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
nbData_LOAD: IN std_logic;
nbData_EN: IN std_logic;
-- LIBRARY RecepteurLIN_lib;
LinSynchro: OUT std_logic;
n_0: OUT std_logic;
nbBit_0: OUT std_logic;
nbData_0: OUT std_logic;
ARCHITECTURE struct OF FrameReceptionOP IS
identifier: OUT std_logic_vector(5 downto 0);
octetRecu: OUT std_logic_vector(7 downto 0)
);
-- Architecture declarations
END receptionTrame_op;
-- Internal signal declarations
SIGNAL BitsNb : std_logic_vector(3 DOWNTO 0);
SIGNAL BitsNb_INIT : std_logic_vector(3 DOWNTO 0);
SIGNAL DataFieldNb_INIT : std_logic_vector(2 DOWNTO 0);
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic_vector(3 DOWNTO 0);
SIGNAL dout2 : std_logic_vector(3 DOWNTO 0);
SIGNAL dout3 : std_logic_vector(10 DOWNTO 0);
SIGNAL dout4 : std_logic_vector(10 DOWNTO 0);
SIGNAL n_INIT : std_logic_vector(10 DOWNTO 0);
SIGNAL pas_n : std_logic_vector(10 DOWNTO 0);
ARCHITECTURE arch OF receptionTrame_op IS
SIGNAL LinSynchro_int : std_logic;
SIGNAL octetRecu_int : std_logic_vector(7 downto 0);
SIGNAL nbDataField_INIT_int : integer := 0;
SIGNAL nbDataField_INIT : unsigned(2 downto 0);
SIGNAL n_INIT : unsigned(n_WIDTH - 1 downto 0);
SIGNAL nbBit_INIT : unsigned(3 downto 0);
-- Implicit buffer signal declarations
SIGNAL LinSynchro_internal : std_logic;
SIGNAL RecByte_internal : std_logic_vector (7 DOWNTO 0);
COMPONENT D_FF
PORT(
H: IN std_logic;
H_EN: IN std_logic;
D: IN std_logic;
nRst: IN std_logic;
Q: OUT std_logic
);
END COMPONENT;
COMPONENT D_FF_BANK IS
PORT(
H: IN std_logic;
H_EN: IN std_logic;
nRst : IN std_logic;
D: IN std_logic_vector;
Q: OUT std_logic_vector
);
END COMPONENT;
-- ModuleWare signal declarations(v1.12) for instance 'U_3' of 'cntr'
SIGNAL mw_U_3n_cnt : std_logic_vector(10 DOWNTO 0);
SIGNAL mw_U_3c_cnt : std_logic_vector(10 DOWNTO 0);
COMPONENT shift_register
GENERIC (
WIDTH: integer
);
PORT(
H: IN std_logic;
H_EN: IN std_logic;
nRst : IN std_logic;
D: IN std_logic;
Q: OUT std_logic_vector
);
END COMPONENT;
-- ModuleWare signal declarations(v1.12) for instance 'U_7' of 'cntr'
SIGNAL mw_U_7n_cnt : std_logic_vector(3 DOWNTO 0);
SIGNAL mw_U_7c_cnt : std_logic_vector(3 DOWNTO 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_13' of 'cntr'
SIGNAL mw_U_13n_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL mw_U_13c_cnt : std_logic_vector(2 DOWNTO 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'dff'
SIGNAL mw_U_0reg_cval : std_logic;
-- ModuleWare signal declarations(v1.12) for instance 'U_11' of 'dff'
SIGNAL mw_U_11reg_cval : std_logic_vector(5 DOWNTO 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_1' of 'shiftsp'
SIGNAL mw_U_1reg_cval : std_logic_vector(7 DOWNTO 0);
SIGNAL mw_U_1reg_nval : std_logic_vector(7 DOWNTO 0);
-- Component Declarations
COMPONENT decoder
PORT (
RecByte : IN std_logic_vector (5 DOWNTO 4);
DataFieldNb_INIT : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
-- FOR ALL : decoder USE ENTITY RecepteurLIN_lib.decoder;
-- pragma synthesis_on
COMPONENT counter
GENERIC(
WIDTH: integer;
MAX_VAL: integer
);
PORT(
H: IN std_logic;
H_EN: IN std_logic;
nRst: IN std_logic;
INIT: IN unsigned(WIDTH-1 downto 0);
LOAD: IN std_logic;
upnDown: IN std_logic;
val: OUT unsigned(WIDTH-1 downto 0);
max: OUT std_logic
);
END COMPONENT;
BEGIN
LinSynchro <= LinSynchro_int;
octetRecu <= octetRecu_int;
-- ModuleWare code(v1.12) for instance 'U_3' of 'cntr'
pas_n <= mw_U_3c_cnt;
u_3clock_proc: PROCESS (H, nCLR)
BEGIN
IF (nCLR = '0') THEN
mw_U_3c_cnt <= "00000000000";
ELSIF (H'EVENT AND H='1') THEN
IF (n_EN = '1') THEN
mw_U_3c_cnt <= mw_U_3n_cnt;
END IF;
END IF;
END PROCESS u_3clock_proc;
u_3combo_proc: PROCESS (n_LOAD, n_INIT, mw_U_3c_cnt)
BEGIN
IF (n_LOAD = '1') THEN
mw_U_3n_cnt <= n_INIT;
ELSE
IF (mw_U_3c_cnt = "00000000000") THEN
mw_U_3n_cnt <= "11111111111";
ELSE
mw_U_3n_cnt <= (unsigned(mw_U_3c_cnt) - '1');
END IF;
END IF;
END PROCESS u_3combo_proc;
u_3max_drive_proc: PROCESS (mw_U_3c_cnt)
BEGIN
n_0 <= '0';
IF (mw_U_3c_cnt = "00000000000") THEN
n_0 <= '1';
END IF;
END PROCESS u_3max_drive_proc;
-- Lin sync D-FF, with asynchronous reset
Lin_in_sync : D_FF
PORT MAP(
H => H,
H_EN => '1',
D => Lin,
nRst => nCLR,
Q => LinSynchro_int
);
-- ModuleWare code(v1.12) for instance 'U_7' of 'cntr'
BitsNb <= mw_U_7c_cnt;
u_7clock_proc: PROCESS (H, nCLR)
BEGIN
IF (nCLR = '0') THEN
mw_U_7c_cnt <= "0000";
ELSIF (H'EVENT AND H='1') THEN
IF (BitsNb_EN = '1') THEN
mw_U_7c_cnt <= mw_U_7n_cnt;
END IF;
END IF;
END PROCESS u_7clock_proc;
u_7combo_proc: PROCESS (BitsNb_LOAD, BitsNb_INIT, mw_U_7c_cnt)
BEGIN
IF (BitsNb_LOAD = '1') THEN
mw_U_7n_cnt <= BitsNb_INIT;
ELSE
IF (mw_U_7c_cnt = "0000") THEN
mw_U_7n_cnt <= "1111";
ELSE
mw_U_7n_cnt <= (unsigned(mw_U_7c_cnt) - '1');
END IF;
END IF;
END PROCESS u_7combo_proc;
u_7max_drive_proc: PROCESS (mw_U_7c_cnt)
BEGIN
BitsNb_0 <= '0';
IF (mw_U_7c_cnt = "0000") THEN
BitsNb_0 <= '1';
END IF;
END PROCESS u_7max_drive_proc;
-- Lin serial->parallel shift reg
Lin_para : shift_register
GENERIC MAP(
WIDTH => 8
)
PORT MAP(
H => H,
H_EN => octetRecu_EN,
nRst => nCLR,
D => LinSynchro_int,
Q => octetRecu_int
);
-- ModuleWare code(v1.12) for instance 'U_13' of 'cntr'
DataFieldNb <= mw_U_13c_cnt;
u_13clock_proc: PROCESS (H, nCLR)
BEGIN
IF (nCLR = '0') THEN
mw_U_13c_cnt <= "000";
ELSIF (H'EVENT AND H='1') THEN
IF (DataFieldNb_EN = '1') THEN
mw_U_13c_cnt <= mw_U_13n_cnt;
END IF;
END IF;
END PROCESS u_13clock_proc;
u_13combo_proc: PROCESS (DataFieldNb_LOAD, DataFieldNb_INIT, mw_U_13c_cnt)
BEGIN
IF (DataFieldNb_LOAD = '1') THEN
mw_U_13n_cnt <= DataFieldNb_INIT;
ELSE
IF (mw_U_13c_cnt = "000") THEN
mw_U_13n_cnt <= "111";
ELSE
mw_U_13n_cnt <= (unsigned(mw_U_13c_cnt) - '1');
END IF;
END IF;
END PROCESS u_13combo_proc;
u_13max_drive_proc: PROCESS (mw_U_13c_cnt)
BEGIN
DataFieldNb_0 <= '0';
IF (mw_U_13c_cnt = "000") THEN
DataFieldNb_0 <= '1';
END IF;
END PROCESS u_13max_drive_proc;
-- Decoder
WITH octetRecu_int(5 downto 4) SELECT
nbDataField_INIT_int <=
1 when "00",
1 when "01",
3 when "10",
7 when "11",
0 when others;
-- ModuleWare code(v1.12) for instance 'U_5' of 'constval'
dout4 <= "10000010001";
nbDataField_INIT <= to_unsigned(nbDataField_INIT_int, 3);
-- ModuleWare code(v1.12) for instance 'U_6' of 'constval'
dout3 <= "01000001001";
-- nbDataField counter
nbDataField_cmp : counter
GENERIC MAP(
WIDTH => 3,
MAX_VAL => 0
)
PORT MAP(
H => H,
H_EN => nbData_EN,
nRst => nCLR,
INIT => nbDataField_INIT,
LOAD => nbData_LOAD,
upnDown => '0',
val => OPEN,
max => nbData_0
);
-- ModuleWare code(v1.12) for instance 'U_9' of 'constval'
dout2 <= "1100";
-- Identifier register
idReg : D_FF_BANK
PORT MAP(
H => H,
H_EN => identifier_EN,
nRst => nClr,
D => octetRecu_int(5 downto 0),
Q => identifier
);
-- ModuleWare code(v1.12) for instance 'U_10' of 'constval'
dout1 <= "1000";
-- n_INIT mux
WITH n_SELECT SELECT
n_INIT <=
to_unsigned(N - 1, N_WIDTH) when '0',
to_unsigned(N / 2, N_WIDTH) when '1',
(others => '0') when others;
-- ModuleWare code(v1.12) for instance 'U_0' of 'dff'
LinSynchro_internal <= mw_U_0reg_cval;
u_0seq_proc: PROCESS (H, nCLR)
BEGIN
IF (nCLR = '0') THEN
mw_U_0reg_cval <= '0';
ELSIF (H'EVENT AND H='1') THEN
mw_U_0reg_cval <= Lin;
END IF;
END PROCESS u_0seq_proc;
-- N counter
N_cmp : counter
GENERIC MAP(
WIDTH => N_WIDTH,
MAX_VAL => 0
)
PORT MAP(
H => H,
H_EN => n_EN,
nRst => nCLR,
INIT => n_INIT,
LOAD => n_LOAD,
upnDown => '0',
val => OPEN,
max => n_0
);
-- ModuleWare code(v1.12) for instance 'U_11' of 'dff'
IdentifierField <= mw_U_11reg_cval;
u_11seq_proc: PROCESS (H, nCLR)
BEGIN
IF (nCLR = '0') THEN
mw_U_11reg_cval <= "000000";
ELSIF (H'EVENT AND H='1') THEN
IF (IdentifierField_EN = '1') THEN
mw_U_11reg_cval <= RecByte_internal(5 DOWNTO 0);
END IF;
END IF;
END PROCESS u_11seq_proc;
-- NbBit mux
with nbBit_SELECT SELECT
nbBit_INIT <=
to_unsigned(13, 4) when '0',
to_unsigned(8, 4) when '1',
to_unsigned(0, 4) when others;
-- ModuleWare code(v1.12) for instance 'U_2' of 'gnd'
dout <= '0';
nbBIt_cmp : counter
GENERIC MAP(
WIDTH => 4,
MAX_VAL => 0
)
PORT MAP(
H => H,
H_EN => nbBit_EN,
nRst => nCLR,
INIT => nbBit_INIT,
LOAD => nbBit_LOAD,
upnDown => '0',
val => OPEN,
max => nbBit_0
);
END ARCHITECTURE arch;
-- ModuleWare code(v1.12) for instance 'U_4' of 'mux'
u_4combo_proc: PROCESS(dout4, dout3, n_SELECT)
BEGIN
CASE n_SELECT IS
WHEN '0' => n_INIT <= dout4;
WHEN '1' => n_INIT <= dout3;
WHEN OTHERS => n_INIT <= (OTHERS => 'X');
END CASE;
END PROCESS u_4combo_proc;
-- ModuleWare code(v1.12) for instance 'U_8' of 'mux'
u_8combo_proc: PROCESS(dout2, dout1, BitsNb_SELECT)
BEGIN
CASE BitsNb_SELECT IS
WHEN '0' => BitsNb_INIT <= dout2;
WHEN '1' => BitsNb_INIT <= dout1;
WHEN OTHERS => BitsNb_INIT <= (OTHERS => 'X');
END CASE;
END PROCESS u_8combo_proc;
-- ModuleWare code(v1.12) for instance 'U_1' of 'shiftsp'
RecByte_internal <= mw_U_1reg_cval;
u_1seq_proc: PROCESS (H, nCLR)
BEGIN
IF (nCLR = '0') THEN
mw_U_1reg_cval <= "00000000";
ELSIF (H'EVENT AND H='1') THEN
IF (RecByte_EN = '1') THEN
mw_U_1reg_cval <= mw_U_1reg_nval;
END IF;
END IF;
END PROCESS u_1seq_proc;
u_1combo_proc: PROCESS (dout, LinSynchro_internal, mw_U_1reg_cval)
VARIABLE temp_dout : std_logic_vector(9 DOWNTO 0);
BEGIN
IF (dout = '0') THEN
temp_dout := LinSynchro_internal & LinSynchro_internal & mw_U_1reg_cval;
ELSIF (dout = '1') THEN
temp_dout := mw_U_1reg_cval & LinSynchro_internal & LinSynchro_internal;
ELSE
temp_dout := (OTHERS => 'X');
END IF;
mw_U_1reg_nval <= temp_dout(8 DOWNTO 1);
END PROCESS u_1combo_proc;
-- Instance port mappings.
U_12 : decoder
PORT MAP (
RecByte => RecByte_internal(5 DOWNTO 4),
DataFieldNb_INIT => DataFieldNb_INIT
);
-- Implicit buffered output assignments
LinSynchro <= LinSynchro_internal;
RecByte <= RecByte_internal;
END struct;

190
ReceptionTrame_lib/receptionTrame_tb.vhd
View File

@ -1,110 +1,106 @@
-- VHDL Entity RecepteurLIN_lib.FrameReception_UnderTest.symbol
--
-- Created:
-- by - e208835U.UNKNOWN (irb121-02)
-- at - 11:35:03 26/09/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY receptionTrame_tb IS
GENERIC(
CLOCK_PERIOD: time := 52 us;
UC_CLK_PERIOD: time := 43 ns
);
END receptionTrame_tb;
ENTITY FrameReception_UnderTest IS
-- Declarations
ARCHITECTURE arch of receptionTrame_tb IS
COMPONENT receptionTrame
PORT(
H: IN std_logic;
nCLR: IN std_logic;
Lin: IN std_logic;
END FrameReception_UnderTest ;
AdrSel: IN std_logic_vector;
--
-- VHDL Architecture RecepteurLIN_lib.FrameReception_UnderTest.struct
--
-- Created:
-- by - e208835u.UNKNOWN (irb013-09)
-- at - 10:39:28 10/10/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
RecByte: OUT std_logic_vector(7 downto 0);
RecByte_WR: OUT std_logic;
RecBytes_RST: OUT std_logic;
-- LIBRARY LIN_Rec_Test_Env_2022_IP;
-- LIBRARY RecepteurLIN_lib;
Err_SET: OUT std_logic_vector(2 downto 0);
NbByteInc: OUT std_logic;
MsgReceived_SET: OUT std_logic;
NbRecByte_RST: OUT std_logic
);
END COMPONENT;
ARCHITECTURE struct OF FrameReception_UnderTest IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL LIN : std_logic;
SIGNAL M_Received : std_logic;
SIGNAL Master_Clk : std_logic;
SIGNAL Reset_bar : std_logic;
-- Component Declarations
COMPONENT LIN_Receiver_Env
GENERIC (
sur_ech : integer
);
PORT (
M_Received : IN std_logic;
C_Dbar : OUT std_logic;
Cs_bar : OUT std_logic;
LIN : OUT std_logic;
Master_Clk : OUT std_logic;
R_Wbar : OUT std_logic;
Reset_bar : OUT std_logic;
Data_Bus : INOUT std_logic_vector ( 7 DOWNTO 0 )
);
END COMPONENT;
COMPONENT FrameReception
PORT (
H : IN std_logic ;
Lin : IN std_logic ;
nRST : IN std_logic ;
RecByte : OUT std_logic_vector (7 DOWNTO 0);
RecByte_RST : OUT std_logic ;
RecByte_WR : OUT std_logic
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
-- FOR ALL : FrameReception USE ENTITY RecepteurLIN_lib.FrameReception;
-- FOR ALL : LIN_Receiver_Env USE ENTITY LIN_Rec_Test_Env_2022_IP.LIN_Receiver_Env;
-- pragma synthesis_on
SIGNAL H: std_logic;
SIGNAL Lin: std_logic;
BEGIN
clkGen : PROCESS
BEGIN
H <= '1';
WAIT FOR UC_CLK_PERIOD / 2;
H <= '0';
WAIT FOR UC_CLK_PERIOD / 2;
END PROCESS clkGen;
-- Instance port mappings.
U_1 : LIN_Receiver_Env
GENERIC MAP (
sur_ech => 1024
)
PORT MAP (
M_Received => M_Received,
C_Dbar => OPEN,
Cs_bar => OPEN,
LIN => LIN,
Master_Clk => Master_Clk,
R_Wbar => OPEN,
Reset_bar => Reset_bar,
Data_Bus => OPEN
);
U_0 : FrameReception
PORT MAP (
H => Master_Clk,
Lin => LIN,
nRST => Reset_bar,
RecByte => OPEN,
RecByte_RST => OPEN,
RecByte_WR => OPEN
);
linFrame : PROCESS
BEGIN
Lin <= '1';
WAIT FOR 100 us;
-- Sync Break
Lin <= '0';
WAIT FOR 14 * CLOCK_PERIOD;
Lin <= '1';
WAIT FOR 2 * CLOCK_PERIOD;
-- Sync field
for i in 4 downto 0 loop
Lin <= '0';
WAIT FOR CLOCK_PERIOD;
Lin <= '1';
WAIT FOR CLOCK_PERIOD;
end loop;
-- ID field (0x0, 2 data byte)
Lin <= '0';
WAIT FOR CLOCK_PERIOD;
Lin <= '0';
WAIT FOR 8 * CLOCK_PERIOD;
Lin <= '1';
WAIT FOR CLOCK_PERIOD;
-- data fields (both 0x00)
Lin <= '0';
WAIT FOR 9 * CLOCK_PERIOD;
Lin <= '1';
WAIT FOR CLOCK_PERIOD;
Lin <= '0';
WAIT FOR 9 * CLOCK_PERIOD;
Lin <= '1';
WAIT FOR CLOCK_PERIOD;
-- checksum (0x0)
Lin <= '0';
WAIT FOR 9 * CLOCK_PERIOD;
Lin <= '1';
WAIT FOR CLOCK_PERIOD;
report "Finished" severity failure ;
END PROCESS;
U0 : receptionTrame
PORT MAP(
H => H,
nCLR => '1',
Lin => Lin,
AdrSel => "000000",
RecByte => OPEN,
RecByte_WR => OPEN,
RecBytes_RST => OPEN,
Err_SET => OPEN,
NbByteInc => OPEN,
MsgReceived_SET => OPEN,
NbRecByte_RST => OPEN
);
END ARCHITECTURE arch;
END struct;

18
fusesoc.conf
View File

@ -4,21 +4,9 @@ sync-uri = https://github.com/fusesoc/fusesoc-cores
sync-type = git
auto-sync = true
[library.InterfaceMicroprocesseur]
location = ./InterfaceMicroprocesseur_lib
sync-uri = InterfaceMicroprocesseur_lib
sync-type = local
auto-sync = true
[library.STDLIB]
location = /home/leo/Sketchbook/VHDL/LIN_receiver/RecepteurLIN_lib/STDLIB_lib
sync-uri = STDLIB_lib
sync-type = local
auto-sync = true
[library.ReceptionTrame]
location = /home/leo/Sketchbook/VHDL/LIN_receiver/RecepteurLIN_lib/ReceptionTrame_lib
sync-uri = ReceptionTrame_lib
[library.recepteurLIN]
location = /home/leo/Sketchbook/VHDL/LIN_receiver/RecepteurLIN_lib
sync-uri = .
sync-type = local
auto-sync = true

178
internalstate_struct.vhd Normal file
View File

@ -0,0 +1,178 @@
-- VHDL Entity RecepteurLIN_lib.InternalState.interface
--
-- Created:
-- by - e208835u.UNKNOWN (irb013-09)
-- at - 12:48:12 17/10/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY InternalState IS
PORT(
Errors_SET : IN std_logic_vector (3 DOWNTO 1);
EtatLu_RST : IN std_logic;
H : IN std_logic;
MessageReceived_SET : IN std_logic;
NbByteDec : IN std_logic;
NbByteInc : IN std_logic;
NbRecByte_RST : IN std_logic;
nCLR : IN std_logic;
EtatLu : OUT std_logic_vector (7 DOWNTO 0)
);
-- Declarations
END InternalState ;
--
-- VHDL Architecture RecepteurLIN_lib.InternalState.struct
--
-- Created:
-- by - e208835u.UNKNOWN (irb013-09)
-- at - 12:48:12 17/10/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE struct OF InternalState IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL dout : std_logic_vector(3 DOWNTO 0);
SIGNAL dout1 : std_logic;
SIGNAL dout2 : std_logic;
-- ModuleWare signal declarations(v1.12) for instance 'U_1' of 'cntr'
SIGNAL mw_U_1n_cnt : std_logic_vector(3 DOWNTO 0);
SIGNAL mw_U_1c_cnt : std_logic_vector(3 DOWNTO 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'rsff'
SIGNAL mw_U_0reg_cval : std_logic;
-- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'rsff'
SIGNAL mw_U_4reg_cval : std_logic;
-- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'rsff'
SIGNAL mw_U_5reg_cval : std_logic;
-- ModuleWare signal declarations(v1.12) for instance 'U_6' of 'rsff'
SIGNAL mw_U_6reg_cval : std_logic;
BEGIN
-- ModuleWare code(v1.12) for instance 'U_1' of 'cntr'
EtatLu(3 DOWNTO 0) <= mw_U_1c_cnt;
u_1clock_proc: PROCESS (H, nCLR)
BEGIN
IF (nCLR = '0') THEN
mw_U_1c_cnt <= "0000";
ELSIF (H'EVENT AND H='1') THEN
IF (dout1 = '1') THEN
mw_U_1c_cnt <= mw_U_1n_cnt;
END IF;
END IF;
END PROCESS u_1clock_proc;
u_1combo_proc: PROCESS (NbRecByte_RST, dout, dout2, mw_U_1c_cnt)
-- up = '1', dn = '0'
BEGIN
IF (NbRecByte_RST = '1') THEN
mw_U_1n_cnt <= dout;
ELSE
IF (dout2 = '1') THEN
IF (mw_U_1c_cnt = "1111") THEN
mw_U_1n_cnt <= (OTHERS => '0');
ELSE
mw_U_1n_cnt <= (unsigned(mw_U_1c_cnt) + '1');
END IF;
ELSE
IF (mw_U_1c_cnt = "0000") THEN
mw_U_1n_cnt <= "1111";
ELSE
mw_U_1n_cnt <= (unsigned(mw_U_1c_cnt) - '1');
END IF;
END IF;
END IF;
END PROCESS u_1combo_proc;
-- ModuleWare code(v1.12) for instance 'U_2' of 'constval'
dout <= "0000";
-- ModuleWare code(v1.12) for instance 'U_7' of 'inv'
dout2 <= NOT(NbByteDec);
-- ModuleWare code(v1.12) for instance 'U_3' of 'or'
dout1 <= NbByteInc OR NbByteDec;
-- ModuleWare code(v1.12) for instance 'U_0' of 'rsff'
EtatLu(4) <= mw_U_0reg_cval;
u_0seq_proc: PROCESS (H, nCLR)
BEGIN
IF (nCLR = '0') THEN
mw_U_0reg_cval <= '0';
ELSIF (H'EVENT AND H='1') THEN
IF (EtatLu_RST = '1') THEN
mw_U_0reg_cval <= '0';
ELSIF (MessageReceived_SET = '1') THEN
mw_U_0reg_cval <= '1';
END IF;
END IF;
END PROCESS u_0seq_proc;
-- ModuleWare code(v1.12) for instance 'U_4' of 'rsff'
EtatLu(7) <= mw_U_4reg_cval;
u_4seq_proc: PROCESS (H, nCLR)
BEGIN
IF (nCLR = '0') THEN
mw_U_4reg_cval <= '0';
ELSIF (H'EVENT AND H='1') THEN
IF (EtatLu_RST = '1') THEN
mw_U_4reg_cval <= '0';
ELSIF (Errors_SET(3) = '1') THEN
mw_U_4reg_cval <= '1';
END IF;
END IF;
END PROCESS u_4seq_proc;
-- ModuleWare code(v1.12) for instance 'U_5' of 'rsff'
EtatLu(6) <= mw_U_5reg_cval;
u_5seq_proc: PROCESS (H, nCLR)
BEGIN
IF (nCLR = '0') THEN
mw_U_5reg_cval <= '0';
ELSIF (H'EVENT AND H='1') THEN
IF (EtatLu_RST = '1') THEN
mw_U_5reg_cval <= '0';
ELSIF (Errors_SET(2) = '1') THEN
mw_U_5reg_cval <= '1';
END IF;
END IF;
END PROCESS u_5seq_proc;
-- ModuleWare code(v1.12) for instance 'U_6' of 'rsff'
EtatLu(5) <= mw_U_6reg_cval;
u_6seq_proc: PROCESS (H, nCLR)
BEGIN
IF (nCLR = '0') THEN
mw_U_6reg_cval <= '0';
ELSIF (H'EVENT AND H='1') THEN
IF (EtatLu_RST = '1') THEN
mw_U_6reg_cval <= '0';
ELSIF (Errors_SET(1) = '1') THEN
mw_U_6reg_cval <= '1';
END IF;
END IF;
END PROCESS u_6seq_proc;
-- Instance port mappings.
END struct;

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-- VHDL Entity RecepteurLIN_lib.RecepteurLIN.symbol
--
-- Created:
-- by - e208835u.UNKNOWN (irb013-09)
-- at - 12:48:09 17/10/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY RecepteurLIN IS
PORT(
CnD : IN std_logic;
H : IN std_logic;
LIN : IN std_logic;
RnW : IN std_logic;
nCLR : IN std_logic;
nCS : IN std_logic;
M_Received : OUT std_logic;
D07 : INOUT std_logic_vector (7 DOWNTO 0)
);
-- Declarations
END RecepteurLIN ;
--
-- VHDL Architecture RecepteurLIN_lib.RecepteurLIN.struct
--
-- Created:
-- by - e208835u.UNKNOWN (irb013-09)
-- at - 12:48:09 17/10/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
-- LIBRARY RecepteurLIN_lib;
ARCHITECTURE struct OF RecepteurLIN IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL Errors_SET : std_logic_vector(3 DOWNTO 1);
SIGNAL EtatLu : std_logic_vector(7 DOWNTO 0);
SIGNAL EtatLu_RST : std_logic;
SIGNAL MessageReceived_SET : std_logic;
SIGNAL NbByteDec : std_logic;
SIGNAL NbByteInc : std_logic;
SIGNAL NbRecByte_RST : std_logic;
SIGNAL RecByte : std_logic_vector(7 DOWNTO 0);
SIGNAL RecByte_RST : std_logic;
SIGNAL RecByte_WR : std_logic;
SIGNAL SelAdr : std_logic_vector(7 DOWNTO 0);
SIGNAL dout : std_logic;
SIGNAL ffout : std_logic_vector(7 DOWNTO 0);
SIGNAL rena : std_logic;
-- ModuleWare signal declarations(v1.12) for instance 'U_1' of 'fifo'
TYPE mw_U_1sreg IS ARRAY (11 DOWNTO 0) OF std_logic_vector(7 DOWNTO 0);
SIGNAL mw_U_1addr_cval : INTEGER RANGE 0 TO 11;
SIGNAL mw_U_1addr_nval : INTEGER RANGE 0 TO 11;
SIGNAL mw_U_1reg_cval : mw_U_1sreg;
SIGNAL mw_U_1reg_nval : mw_U_1sreg;
-- Component Declarations
COMPONENT FrameReception
PORT (
H : IN std_logic ;
Lin : IN std_logic ;
SelAdr : IN std_logic_vector (7 DOWNTO 0);
nRST : IN std_logic ;
ErrorSet : OUT std_logic_vector (3 DOWNTO 1);
MsgRcv_SET : OUT std_logic ;
NbRecByte_Inc : OUT std_logic ;
RecByte : OUT std_logic_vector (7 DOWNTO 0);
RecByte_RST : OUT std_logic ;
RecByte_WR : OUT std_logic
);
END COMPONENT;
COMPONENT InterfaceMicroprocesseur
PORT (
CnD : IN std_logic ;
EtatLu : IN std_logic_vector (7 DOWNTO 0);
H : IN std_logic ;
OctetLu : IN std_logic_vector (7 DOWNTO 0);
RnW : IN std_logic ;
nCS : IN std_logic ;
nRST : IN std_logic ;
DecNbOctet : OUT std_logic ;
EtatLu_RST : OUT std_logic ;
M_Received : OUT std_logic ;
OctetLu_RD : OUT std_logic ;
SelAdr : OUT std_logic_vector (7 DOWNTO 0);
D07 : INOUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT InternalState
PORT (
Errors_SET : IN std_logic_vector (3 DOWNTO 1);
EtatLu_RST : IN std_logic ;
H : IN std_logic ;
MessageReceived_SET : IN std_logic ;
NbByteDec : IN std_logic ;
NbByteInc : IN std_logic ;
NbRecByte_RST : IN std_logic ;
nCLR : IN std_logic ;
EtatLu : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
-- FOR ALL : FrameReception USE ENTITY RecepteurLIN_lib.FrameReception;
-- FOR ALL : InterfaceMicroprocesseur USE ENTITY RecepteurLIN_lib.InterfaceMicroprocesseur;
-- FOR ALL : InternalState USE ENTITY RecepteurLIN_lib.InternalState;
-- pragma synthesis_on
BEGIN
-- ModuleWare code(v1.12) for instance 'U_1' of 'fifo'
ffout <= mw_U_1reg_cval(0);
u_1seq1_proc: PROCESS (H)
BEGIN
IF (H'EVENT AND H='1') THEN
FOR i IN 0 TO 11 LOOP
mw_U_1reg_cval(i)(7 DOWNTO 0) <= mw_U_1reg_nval(i)(7 DOWNTO 0);
END LOOP;
END IF;
END PROCESS u_1seq1_proc;
u_1seq2_proc: PROCESS (H, dout)
BEGIN
IF (dout = '1') THEN
mw_U_1addr_cval <= 0;
ELSIF (H'EVENT AND H='1') THEN
mw_U_1addr_cval <= mw_U_1addr_nval;
END IF;
END PROCESS u_1seq2_proc;
u_1combo_proc: PROCESS (dout, rena, RecByte_WR, mw_U_1addr_cval, mw_U_1reg_cval, RecByte)
VARIABLE temp_rena : std_logic;
VARIABLE temp_wena : std_logic;
VARIABLE temp_full : std_logic;
VARIABLE temp_empty : std_logic;
BEGIN
IF (mw_U_1addr_cval = 11) THEN
temp_full := '1';
temp_empty := '0';
ELSIF (mw_U_1addr_cval = 0) THEN
temp_full := '0';
temp_empty := '1';
ELSE
temp_full := '0';
temp_empty := '0';
END IF;
temp_rena := NOT(dout) AND rena AND NOT(temp_empty);
temp_wena := NOT(dout) AND RecByte_WR AND NOT(temp_full);
IF (temp_wena = '1') THEN
mw_U_1addr_nval <= mw_U_1addr_cval + 1;
ELSIF (temp_rena = '1') THEN
mw_U_1addr_nval <= mw_U_1addr_cval - 1;
ELSE
mw_U_1addr_nval <= mw_U_1addr_cval;
END IF;
IF (temp_wena = '1') THEN
mw_U_1reg_nval(0)(7 DOWNTO 0) <= mw_U_1reg_cval(0)(7 DOWNTO 0);
FOR i IN 0 TO 10 LOOP
IF (mw_U_1addr_cval = i) THEN
mw_U_1reg_nval(i+1)(7 DOWNTO 0) <= RecByte;
ELSE
mw_U_1reg_nval(i+1)(7 DOWNTO 0) <= mw_U_1reg_cval(i+1)(7 DOWNTO 0);
END IF;
END LOOP;
ELSIF (temp_wena = '0') THEN
IF (temp_rena = '1') THEN
FOR i IN 0 TO 10 LOOP
mw_U_1reg_nval(i)(7 DOWNTO 0) <= mw_U_1reg_cval(i+1)(7 DOWNTO 0);
END LOOP;
mw_U_1reg_nval(11)(7 DOWNTO 0) <= mw_U_1reg_cval(11)(7 DOWNTO 0);
ELSIF (temp_rena = '0') THEN
FOR i IN 0 TO 11 LOOP
mw_U_1reg_nval(i)(7 DOWNTO 0) <= mw_U_1reg_cval(i)(7 DOWNTO 0);
END LOOP;
ELSE
FOR i IN 0 TO 11 LOOP
mw_U_1reg_nval(i)(7 DOWNTO 0) <= (OTHERS => 'X');
END LOOP;
END IF;
ELSE
FOR i IN 0 TO 11 LOOP
mw_U_1reg_nval(i)(7 DOWNTO 0) <= (OTHERS => 'X');
END LOOP;
END IF;
END PROCESS u_1combo_proc;
-- ModuleWare code(v1.12) for instance 'U_4' of 'pbuf'
u_4seq_proc: PROCESS (RecByte_RST)
BEGIN
IF (RecByte_RST ='1' ) THEN
dout <= '1';
ELSIF (RecByte_RST ='H' ) THEN
dout <= '1';
ELSIF (RecByte_RST ='0' ) THEN
dout <= '0';
ELSIF (RecByte_RST ='L' ) THEN
dout <= '0';
ELSIF (RecByte_RST ='U' ) THEN
dout <= 'U';
ELSIF (RecByte_RST ='X' ) THEN
dout <= 'X';
ELSIF (RecByte_RST ='Z' ) THEN
dout <= 'X';
END IF;
END PROCESS u_4seq_proc;
-- ModuleWare code(v1.12) for instance 'U_5' of 'pbuf'
u_5seq_proc: PROCESS (RecByte_RST)
BEGIN
IF (RecByte_RST ='1' ) THEN
NbRecByte_RST <= '1';
ELSIF (RecByte_RST ='H' ) THEN
NbRecByte_RST <= '1';
ELSIF (RecByte_RST ='0' ) THEN
NbRecByte_RST <= '0';
ELSIF (RecByte_RST ='L' ) THEN
NbRecByte_RST <= '0';
ELSIF (RecByte_RST ='U' ) THEN
NbRecByte_RST <= 'U';
ELSIF (RecByte_RST ='X' ) THEN
NbRecByte_RST <= 'X';
ELSIF (RecByte_RST ='Z' ) THEN
NbRecByte_RST <= 'X';
END IF;
END PROCESS u_5seq_proc;
-- Instance port mappings.
U_2 : FrameReception
PORT MAP (
H => H,
Lin => LIN,
SelAdr => SelAdr,
nRST => nCLR,
ErrorSet => Errors_SET,
MsgRcv_SET => MessageReceived_SET,
NbRecByte_Inc => NbByteInc,
RecByte => RecByte,
RecByte_RST => RecByte_RST,
RecByte_WR => RecByte_WR
);
U_0 : InterfaceMicroprocesseur
PORT MAP (
CnD => CnD,
EtatLu => EtatLu,
H => H,
OctetLu => ffout,
RnW => RnW,
nCS => nCS,
nRST => nCLR,
DecNbOctet => NbByteDec,
EtatLu_RST => EtatLu_RST,
M_Received => M_Received,
OctetLu_RD => rena,
SelAdr => SelAdr,
D07 => D07
);
U_3 : InternalState
PORT MAP (
Errors_SET => Errors_SET,
EtatLu_RST => EtatLu_RST,
H => H,
MessageReceived_SET => MessageReceived_SET,
NbByteDec => NbByteDec,
NbByteInc => NbByteInc,
NbRecByte_RST => NbRecByte_RST,
nCLR => nCLR,
EtatLu => EtatLu
);
END struct;

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-- VHDL Entity RecepteurLIN_lib.RecepteurLin_UnderTest.symbol
--
-- Created:
-- by - e208835u.UNKNOWN (irb013-09)
-- at - 10:50:04 10/10/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY RecepteurLin_UnderTest IS
-- Declarations
END RecepteurLin_UnderTest ;
--
-- VHDL Architecture RecepteurLIN_lib.RecepteurLin_UnderTest.struct
--
-- Created:
-- by - e208835u.UNKNOWN (irb013-09)
-- at - 10:39:26 17/10/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
-- LIBRARY LIN_Rec_Test_Env_2022_IP;
-- LIBRARY RecepteurLIN_lib;
ARCHITECTURE struct OF RecepteurLin_UnderTest IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL C_Dbar : std_logic;
SIGNAL Cs_bar : std_logic;
SIGNAL Data_Bus : std_logic_vector( 7 DOWNTO 0 );
SIGNAL LIN : std_logic;
SIGNAL M_Received : std_logic;
SIGNAL Master_Clk : std_logic;
SIGNAL R_Wbar : std_logic;
SIGNAL Reset_bar : std_logic;
-- Component Declarations
COMPONENT LIN_Receiver_Env
GENERIC (
sur_ech : integer
);
PORT (
M_Received : IN std_logic;
C_Dbar : OUT std_logic;
Cs_bar : OUT std_logic;
LIN : OUT std_logic;
Master_Clk : OUT std_logic;
R_Wbar : OUT std_logic;
Reset_bar : OUT std_logic;
Data_Bus : INOUT std_logic_vector ( 7 DOWNTO 0 )
);
END COMPONENT;
COMPONENT RecepteurLIN
PORT (
CnD : IN std_logic ;
H : IN std_logic ;
LIN : IN std_logic ;
RnW : IN std_logic ;
nCLR : IN std_logic ;
nCS : IN std_logic ;
M_Received : OUT std_logic ;
D07 : INOUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
-- FOR ALL : LIN_Receiver_Env USE ENTITY LIN_Rec_Test_Env_2022_IP.LIN_Receiver_Env;
-- FOR ALL : RecepteurLIN USE ENTITY RecepteurLIN_lib.RecepteurLIN;
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
U_1 : LIN_Receiver_Env
GENERIC MAP (
sur_ech => 1024
)
PORT MAP (
M_Received => M_Received,
C_Dbar => C_Dbar,
Cs_bar => Cs_bar,
LIN => LIN,
Master_Clk => Master_Clk,
R_Wbar => R_Wbar,
Reset_bar => Reset_bar,
Data_Bus => Data_Bus
);
U_0 : RecepteurLIN
PORT MAP (
CnD => C_Dbar,
H => Master_Clk,
LIN => LIN,
RnW => R_Wbar,
nCLR => Reset_bar,
nCS => Cs_bar,
M_Received => M_Received,
D07 => Data_Bus
);
END struct;